Searched refs:HAL_SEQ_WCSS_UMAC_CE0_SRC_REG (Results 1 – 6 of 6) sorted by relevance
569 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()570 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_qcn9274()572 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; in ath12k_hal_srng_create_config_qcn9274()574 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; in ath12k_hal_srng_create_config_qcn9274()1010 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_wcn7850()1011 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_wcn7850()1013 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; in ath12k_hal_srng_create_config_wcn7850()1015 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; in ath12k_hal_srng_create_config_wcn7850()
47 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x01b80000 macro
1223 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB + in ath11k_hal_srng_create_config()1225 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP + in ath11k_hal_srng_create_config()1228 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); in ath11k_hal_srng_create_config()1230 HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); in ath11k_hal_srng_create_config()
46 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) \ macro
61 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) < in ath11k_pci_get_window_start()
157 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) < in ath11k_ahb_get_window_start_wcn6750()
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