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Searched refs:HAL_SEQ_WCSS_UMAC_TCL_REG (Results 1 – 6 of 6) sorted by relevance

/linux-6.3-rc2/drivers/net/wireless/ath/ath12k/
A Dhal_tx.c77 ctrl_reg_val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath12k_hal_tx_set_dscp_tid_map()
81 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath12k_hal_tx_set_dscp_tid_map()
84 addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP + in ath12k_hal_tx_set_dscp_tid_map()
132 ctrl_reg_val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath12k_hal_tx_set_dscp_tid_map()
135 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath12k_hal_tx_set_dscp_tid_map()
A Dhal.c555 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()
556 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
561 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
562 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
566 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
619 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
995 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB; in ath12k_hal_srng_create_config_wcn7850()
996 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1001 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1002 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
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A Dhal.h46 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 macro
/linux-6.3-rc2/drivers/net/wireless/ath/ath11k/
A Dhal_tx.c92 ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath11k_hal_tx_set_dscp_tid_map()
96 ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath11k_hal_tx_set_dscp_tid_map()
99 addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP + in ath11k_hal_tx_set_dscp_tid_map()
132 ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath11k_hal_tx_set_dscp_tid_map()
135 ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + in ath11k_hal_tx_set_dscp_tid_map()
A Dhal.c1209 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()
1210 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; in ath11k_hal_srng_create_config()
1215 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()
1216 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; in ath11k_hal_srng_create_config()
1219 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab); in ath11k_hal_srng_create_config()
1220 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; in ath11k_hal_srng_create_config()
A Dhal.h45 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 macro

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