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Searched refs:HCLK_NANDC (Results 1 – 24 of 24) sorted by relevance

/linux-6.3-rc2/include/dt-bindings/clock/
A Drk3036-cru.h83 #define HCLK_NANDC 453 macro
A Drk3128-cru.h127 #define HCLK_NANDC 453 macro
A Drk3228-cru.h125 #define HCLK_NANDC 453 macro
A Drv1108-cru.h142 #define HCLK_NANDC 323 macro
A Dpx30-cru.h130 #define HCLK_NANDC 254 macro
A Drk3308-cru.h147 #define HCLK_NANDC 153 macro
A Drk3328-cru.h178 #define HCLK_NANDC 316 macro
A Drockchip,rv1126-cru.h297 #define HCLK_NANDC 233 macro
A Drk3568-cru.h179 #define HCLK_NANDC 116 macro
/linux-6.3-rc2/Documentation/devicetree/bindings/mtd/
A Drockchip,nand-controller.yaml137 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
/linux-6.3-rc2/drivers/clk/rockchip/
A Dclk-rk3036.c400 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
A Dclk-rk3128.c501 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(5), 9, GFLAGS),
A Dclk-rk3228.c562 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
A Dclk-rv1108.c737 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
A Dclk-px30.c891 GATE(HCLK_NANDC, "hclk_nandc", "hclk_mmc_nand", 0, PX30_CLKGATE_CON(5), 15, GFLAGS),
A Dclk-rk3308.c820 GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK3308_CLKGATE_CON(9), 6, GFLAGS),
A Dclk-rv1126.c757 GATE(HCLK_NANDC, "hclk_nandc", "hclk_pdnvm", 0,
A Dclk-rk3568.c774 GATE(HCLK_NANDC, "hclk_nandc", "hclk_secure_flash", 0,
/linux-6.3-rc2/arch/arm/boot/dts/
A Drv1126.dtsi155 <&cru HCLK_NANDC>,
A Drk3036.dtsi318 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
A Drk3128.dtsi178 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
A Drv1108.dtsi463 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
/linux-6.3-rc2/arch/arm64/boot/dts/rockchip/
A Dpx30.dtsi294 clocks = <&cru HCLK_NANDC>,
1049 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
A Drk3308.dtsi703 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;

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