1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_SH_HD64461
3 #define __ASM_SH_HD64461
4 /*
5  *	Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
6  *	Copyright (C) 2004 Paul Mundt
7  *	Copyright (C) 2000 YAEGASHI Takeshi
8  *
9  *		Hitachi HD64461 companion chip support
10  *	(please note manual reference 0x10000000 = 0xb0000000)
11  */
12 
13 /* Constants for PCMCIA mappings */
14 #define	HD64461_PCC_WINDOW	0x01000000
15 
16 /* Area 6 - Slot 0 - memory and/or IO card */
17 #define HD64461_IOBASE		0xb0000000
18 #define HD64461_IO_OFFSET(x)	(HD64461_IOBASE + (x))
19 #define	HD64461_PCC0_BASE	HD64461_IO_OFFSET(0x8000000)
20 #define	HD64461_PCC0_ATTR	(HD64461_PCC0_BASE)				/* 0xb80000000 */
21 #define	HD64461_PCC0_COMM	(HD64461_PCC0_BASE+HD64461_PCC_WINDOW)		/* 0xb90000000 */
22 #define	HD64461_PCC0_IO		(HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW)	/* 0xba0000000 */
23 
24 /* Area 5 - Slot 1 - memory card only */
25 #define	HD64461_PCC1_BASE	HD64461_IO_OFFSET(0x4000000)
26 #define	HD64461_PCC1_ATTR	(HD64461_PCC1_BASE)				/* 0xb4000000 */
27 #define	HD64461_PCC1_COMM	(HD64461_PCC1_BASE+HD64461_PCC_WINDOW)		/* 0xb5000000 */
28 
29 /* Standby Control Register for HD64461 */
30 #define	HD64461_STBCR			HD64461_IO_OFFSET(0x00000000)
31 #define	HD64461_STBCR_CKIO_STBY		0x2000
32 #define	HD64461_STBCR_SAFECKE_IST	0x1000
33 #define	HD64461_STBCR_SLCKE_IST		0x0800
34 #define	HD64461_STBCR_SAFECKE_OST	0x0400
35 #define	HD64461_STBCR_SLCKE_OST		0x0200
36 #define	HD64461_STBCR_SMIAST		0x0100
37 #define	HD64461_STBCR_SLCDST		0x0080
38 #define	HD64461_STBCR_SPC0ST		0x0040
39 #define	HD64461_STBCR_SPC1ST		0x0020
40 #define	HD64461_STBCR_SAFEST		0x0010
41 #define	HD64461_STBCR_STM0ST		0x0008
42 #define	HD64461_STBCR_STM1ST		0x0004
43 #define	HD64461_STBCR_SIRST		0x0002
44 #define	HD64461_STBCR_SURTST		0x0001
45 
46 /* System Configuration Register */
47 #define	HD64461_SYSCR		HD64461_IO_OFFSET(0x02)
48 
49 /* CPU Data Bus Control Register */
50 #define	HD64461_SCPUCR		HD64461_IO_OFFSET(0x04)
51 
52 /* Base Address Register */
53 #define	HD64461_LCDCBAR		HD64461_IO_OFFSET(0x1000)
54 
55 /* Line increment address */
56 #define	HD64461_LCDCLOR		HD64461_IO_OFFSET(0x1002)
57 
58 /* Controls LCD controller */
59 #define	HD64461_LCDCCR		HD64461_IO_OFFSET(0x1004)
60 
61 /* LCCDR control bits */
62 #define	HD64461_LCDCCR_STBACK	0x0400	/* Standby Back */
63 #define	HD64461_LCDCCR_STREQ	0x0100	/* Standby Request */
64 #define	HD64461_LCDCCR_MOFF	0x0080	/* Memory Off */
65 #define	HD64461_LCDCCR_REFSEL	0x0040	/* Refresh Select */
66 #define	HD64461_LCDCCR_EPON	0x0020	/* End Power On */
67 #define	HD64461_LCDCCR_SPON	0x0010	/* Start Power On */
68 
69 /* Controls LCD (1) */
70 #define	HD64461_LDR1		HD64461_IO_OFFSET(0x1010)
71 #define	HD64461_LDR1_DON	0x01	/* Display On */
72 #define	HD64461_LDR1_DINV	0x80	/* Display Invert */
73 
74 /* Controls LCD (2) */
75 #define	HD64461_LDR2		HD64461_IO_OFFSET(0x1012)
76 #define	HD64461_LDHNCR		HD64461_IO_OFFSET(0x1014)	/* Number of horizontal characters */
77 #define	HD64461_LDHNSR		HD64461_IO_OFFSET(0x1016)	/* Specify output start position + width of CL1 */
78 #define	HD64461_LDVNTR		HD64461_IO_OFFSET(0x1018)	/* Specify total vertical lines */
79 #define	HD64461_LDVNDR		HD64461_IO_OFFSET(0x101a)	/* specify number of display vertical lines */
80 #define	HD64461_LDVSPR		HD64461_IO_OFFSET(0x101c)	/* specify vertical synchronization pos and AC nr */
81 
82 /* Controls LCD (3) */
83 #define	HD64461_LDR3		HD64461_IO_OFFSET(0x101e)
84 
85 /* Palette Registers */
86 #define	HD64461_CPTWAR		HD64461_IO_OFFSET(0x1030)	/* Color Palette Write Address Register */
87 #define	HD64461_CPTWDR		HD64461_IO_OFFSET(0x1032)	/* Color Palette Write Data Register */
88 #define	HD64461_CPTRAR		HD64461_IO_OFFSET(0x1034)	/* Color Palette Read Address Register */
89 #define	HD64461_CPTRDR		HD64461_IO_OFFSET(0x1036)	/* Color Palette Read Data Register */
90 
91 #define	HD64461_GRDOR		HD64461_IO_OFFSET(0x1040)	/* Display Resolution Offset Register */
92 #define	HD64461_GRSCR		HD64461_IO_OFFSET(0x1042)	/* Solid Color Register */
93 #define	HD64461_GRCFGR		HD64461_IO_OFFSET(0x1044)	/* Accelerator Configuration Register */
94 
95 #define	HD64461_GRCFGR_ACCSTATUS	0x10	/* Accelerator Status */
96 #define	HD64461_GRCFGR_ACCRESET		0x08	/* Accelerator Reset */
97 #define	HD64461_GRCFGR_ACCSTART_BITBLT	0x06	/* Accelerator Start BITBLT */
98 #define	HD64461_GRCFGR_ACCSTART_LINE	0x04	/* Accelerator Start Line Drawing */
99 #define	HD64461_GRCFGR_COLORDEPTH16	0x01	/* Sets Colordepth 16 for Accelerator */
100 #define	HD64461_GRCFGR_COLORDEPTH8	0x01	/* Sets Colordepth 8 for Accelerator */
101 
102 /* Line Drawing Registers */
103 #define	HD64461_LNSARH		HD64461_IO_OFFSET(0x1046)	/* Line Start Address Register (H) */
104 #define	HD64461_LNSARL		HD64461_IO_OFFSET(0x1048)	/* Line Start Address Register (L) */
105 #define	HD64461_LNAXLR		HD64461_IO_OFFSET(0x104a)	/* Axis Pixel Length Register */
106 #define	HD64461_LNDGR		HD64461_IO_OFFSET(0x104c)	/* Diagonal Register */
107 #define	HD64461_LNAXR		HD64461_IO_OFFSET(0x104e)	/* Axial Register */
108 #define	HD64461_LNERTR		HD64461_IO_OFFSET(0x1050)	/* Start Error Term Register */
109 #define	HD64461_LNMDR		HD64461_IO_OFFSET(0x1052)	/* Line Mode Register */
110 
111 /* BitBLT Registers */
112 #define	HD64461_BBTSSARH	HD64461_IO_OFFSET(0x1054)	/* Source Start Address Register (H) */
113 #define	HD64461_BBTSSARL	HD64461_IO_OFFSET(0x1056)	/* Source Start Address Register (L) */
114 #define	HD64461_BBTDSARH	HD64461_IO_OFFSET(0x1058)	/* Destination Start Address Register (H) */
115 #define	HD64461_BBTDSARL	HD64461_IO_OFFSET(0x105a)	/* Destination Start Address Register (L) */
116 #define	HD64461_BBTDWR		HD64461_IO_OFFSET(0x105c)	/* Destination Block Width Register */
117 #define	HD64461_BBTDHR		HD64461_IO_OFFSET(0x105e)	/* Destination Block Height Register */
118 #define	HD64461_BBTPARH		HD64461_IO_OFFSET(0x1060)	/* Pattern Start Address Register (H) */
119 #define	HD64461_BBTPARL		HD64461_IO_OFFSET(0x1062)	/* Pattern Start Address Register (L) */
120 #define	HD64461_BBTMARH		HD64461_IO_OFFSET(0x1064)	/* Mask Start Address Register (H) */
121 #define	HD64461_BBTMARL		HD64461_IO_OFFSET(0x1066)	/* Mask Start Address Register (L) */
122 #define	HD64461_BBTROPR		HD64461_IO_OFFSET(0x1068)	/* ROP Register */
123 #define	HD64461_BBTMDR		HD64461_IO_OFFSET(0x106a)	/* BitBLT Mode Register */
124 
125 /* PC Card Controller Registers */
126 /* Maps to Physical Area 6 */
127 #define	HD64461_PCC0ISR		HD64461_IO_OFFSET(0x2000)	/* socket 0 interface status */
128 #define	HD64461_PCC0GCR		HD64461_IO_OFFSET(0x2002)	/* socket 0 general control */
129 #define	HD64461_PCC0CSCR	HD64461_IO_OFFSET(0x2004)	/* socket 0 card status change */
130 #define	HD64461_PCC0CSCIER	HD64461_IO_OFFSET(0x2006)	/* socket 0 card status change interrupt enable */
131 #define	HD64461_PCC0SCR		HD64461_IO_OFFSET(0x2008)	/* socket 0 software control */
132 /* Maps to Physical Area 5 */
133 #define	HD64461_PCC1ISR		HD64461_IO_OFFSET(0x2010)	/* socket 1 interface status */
134 #define	HD64461_PCC1GCR		HD64461_IO_OFFSET(0x2012)	/* socket 1 general control */
135 #define	HD64461_PCC1CSCR	HD64461_IO_OFFSET(0x2014)	/* socket 1 card status change */
136 #define	HD64461_PCC1CSCIER	HD64461_IO_OFFSET(0x2016)	/* socket 1 card status change interrupt enable */
137 #define	HD64461_PCC1SCR		HD64461_IO_OFFSET(0x2018)	/* socket 1 software control */
138 
139 /* PCC Interface Status Register */
140 #define	HD64461_PCCISR_READY		0x80	/* card ready */
141 #define	HD64461_PCCISR_MWP		0x40	/* card write-protected */
142 #define	HD64461_PCCISR_VS2		0x20	/* voltage select pin 2 */
143 #define	HD64461_PCCISR_VS1		0x10	/* voltage select pin 1 */
144 #define	HD64461_PCCISR_CD2		0x08	/* card detect 2 */
145 #define	HD64461_PCCISR_CD1		0x04	/* card detect 1 */
146 #define	HD64461_PCCISR_BVD2		0x02	/* battery 1 */
147 #define	HD64461_PCCISR_BVD1		0x01	/* battery 1 */
148 
149 #define	HD64461_PCCISR_PCD_MASK		0x0c	/* card detect */
150 #define	HD64461_PCCISR_BVD_MASK		0x03	/* battery voltage */
151 #define	HD64461_PCCISR_BVD_BATGOOD	0x03	/* battery good */
152 #define	HD64461_PCCISR_BVD_BATWARN	0x01	/* battery low warning */
153 #define	HD64461_PCCISR_BVD_BATDEAD1	0x02	/* battery dead */
154 #define	HD64461_PCCISR_BVD_BATDEAD2	0x00	/* battery dead */
155 
156 /* PCC General Control Register */
157 #define	HD64461_PCCGCR_DRVE		0x80	/* output drive */
158 #define	HD64461_PCCGCR_PCCR		0x40	/* PC card reset */
159 #define	HD64461_PCCGCR_PCCT		0x20	/* PC card type, 1=IO&mem, 0=mem */
160 #define	HD64461_PCCGCR_VCC0		0x10	/* voltage control pin VCC0SEL0 */
161 #define	HD64461_PCCGCR_PMMOD		0x08	/* memory mode */
162 #define	HD64461_PCCGCR_PA25		0x04	/* pin A25 */
163 #define	HD64461_PCCGCR_PA24		0x02	/* pin A24 */
164 #define	HD64461_PCCGCR_REG		0x01	/* pin PCC0REG# */
165 
166 /* PCC Card Status Change Register */
167 #define	HD64461_PCCCSCR_SCDI		0x80	/* sw card detect intr */
168 #define	HD64461_PCCCSCR_SRV1		0x40	/* reserved */
169 #define	HD64461_PCCCSCR_IREQ		0x20	/* IREQ intr req */
170 #define	HD64461_PCCCSCR_SC		0x10	/* STSCHG (status change) pin */
171 #define	HD64461_PCCCSCR_CDC		0x08	/* CD (card detect) change */
172 #define	HD64461_PCCCSCR_RC		0x04	/* READY change */
173 #define	HD64461_PCCCSCR_BW		0x02	/* battery warning change */
174 #define	HD64461_PCCCSCR_BD		0x01	/* battery dead change */
175 
176 /* PCC Card Status Change Interrupt Enable Register */
177 #define	HD64461_PCCCSCIER_CRE		0x80	/* change reset enable */
178 #define	HD64461_PCCCSCIER_IREQE_MASK	0x60	/* IREQ enable */
179 #define	HD64461_PCCCSCIER_IREQE_DISABLED 0x00	/* IREQ disabled */
180 #define	HD64461_PCCCSCIER_IREQE_LEVEL	0x20	/* IREQ level-triggered */
181 #define	HD64461_PCCCSCIER_IREQE_FALLING	0x40	/* IREQ falling-edge-trig */
182 #define	HD64461_PCCCSCIER_IREQE_RISING	0x60	/* IREQ rising-edge-trig */
183 
184 #define	HD64461_PCCCSCIER_SCE		0x10	/* status change enable */
185 #define	HD64461_PCCCSCIER_CDE		0x08	/* card detect change enable */
186 #define	HD64461_PCCCSCIER_RE		0x04	/* ready change enable */
187 #define	HD64461_PCCCSCIER_BWE		0x02	/* battery warn change enable */
188 #define	HD64461_PCCCSCIER_BDE		0x01	/* battery dead change enable*/
189 
190 /* PCC Software Control Register */
191 #define	HD64461_PCCSCR_VCC1		0x02	/* voltage control pin 1 */
192 #define	HD64461_PCCSCR_SWP		0x01	/* write protect */
193 
194 /* PCC0 Output Pins Control Register */
195 #define	HD64461_P0OCR		HD64461_IO_OFFSET(0x202a)
196 
197 /* PCC1 Output Pins Control Register */
198 #define	HD64461_P1OCR		HD64461_IO_OFFSET(0x202c)
199 
200 /* PC Card General Control Register */
201 #define	HD64461_PGCR		HD64461_IO_OFFSET(0x202e)
202 
203 /* Port Control Registers */
204 #define	HD64461_GPACR		HD64461_IO_OFFSET(0x4000)	/* Port A - Handles IRDA/TIMER */
205 #define	HD64461_GPBCR		HD64461_IO_OFFSET(0x4002)	/* Port B - Handles UART */
206 #define	HD64461_GPCCR		HD64461_IO_OFFSET(0x4004)	/* Port C - Handles PCMCIA 1 */
207 #define	HD64461_GPDCR		HD64461_IO_OFFSET(0x4006)	/* Port D - Handles PCMCIA 1 */
208 
209 /* Port Control Data Registers */
210 #define	HD64461_GPADR		HD64461_IO_OFFSET(0x4010)	/* A */
211 #define	HD64461_GPBDR		HD64461_IO_OFFSET(0x4012)	/* B */
212 #define	HD64461_GPCDR		HD64461_IO_OFFSET(0x4014)	/* C */
213 #define	HD64461_GPDDR		HD64461_IO_OFFSET(0x4016)	/* D */
214 
215 /* Interrupt Control Registers */
216 #define	HD64461_GPAICR		HD64461_IO_OFFSET(0x4020)	/* A */
217 #define	HD64461_GPBICR		HD64461_IO_OFFSET(0x4022)	/* B */
218 #define	HD64461_GPCICR		HD64461_IO_OFFSET(0x4024)	/* C */
219 #define	HD64461_GPDICR		HD64461_IO_OFFSET(0x4026)	/* D */
220 
221 /* Interrupt Status Registers */
222 #define	HD64461_GPAISR		HD64461_IO_OFFSET(0x4040)	/* A */
223 #define	HD64461_GPBISR		HD64461_IO_OFFSET(0x4042)	/* B */
224 #define	HD64461_GPCISR		HD64461_IO_OFFSET(0x4044)	/* C */
225 #define	HD64461_GPDISR		HD64461_IO_OFFSET(0x4046)	/* D */
226 
227 /* Interrupt Request Register & Interrupt Mask Register */
228 #define	HD64461_NIRR		HD64461_IO_OFFSET(0x5000)
229 #define	HD64461_NIMR		HD64461_IO_OFFSET(0x5002)
230 
231 #define	HD64461_IRQBASE		OFFCHIP_IRQ_BASE
232 #define	OFFCHIP_IRQ_BASE	64
233 #define	HD64461_IRQ_NUM		16
234 
235 #define	HD64461_IRQ_UART	(HD64461_IRQBASE+5)
236 #define	HD64461_IRQ_IRDA	(HD64461_IRQBASE+6)
237 #define	HD64461_IRQ_TMU1	(HD64461_IRQBASE+9)
238 #define	HD64461_IRQ_TMU0	(HD64461_IRQBASE+10)
239 #define	HD64461_IRQ_GPIO	(HD64461_IRQBASE+11)
240 #define	HD64461_IRQ_AFE		(HD64461_IRQBASE+12)
241 #define	HD64461_IRQ_PCC1	(HD64461_IRQBASE+13)
242 #define	HD64461_IRQ_PCC0	(HD64461_IRQBASE+14)
243 
244 #define __IO_PREFIX	hd64461
245 #include <asm/io_generic.h>
246 
247 /* arch/sh/cchips/hd6446x/hd64461/setup.c */
248 void hd64461_register_irq_demux(int irq,
249 				int (*demux) (int irq, void *dev), void *dev);
250 void hd64461_unregister_irq_demux(int irq);
251 
252 #endif
253