Searched refs:HEVC_ENC_CMD_FLUSH_TLB (Results 1 – 2 of 2) sorted by relevance
476 #define HEVC_ENC_CMD_FLUSH_TLB 0x00000108 macro
1138 amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB); in uvd_v6_0_enc_ring_emit_vm_flush()
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