1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File hw_atl_a0_internal.h: Definition of Atlantic A0 chip specific 8 * constants. 9 */ 10 11 #ifndef HW_ATL_A0_INTERNAL_H 12 #define HW_ATL_A0_INTERNAL_H 13 14 #include "../aq_common.h" 15 16 #define HW_ATL_A0_MTU_JUMBO 9014U 17 18 #define HW_ATL_A0_TX_RINGS 4U 19 #define HW_ATL_A0_RX_RINGS 4U 20 21 #define HW_ATL_A0_RINGS_MAX 32U 22 #define HW_ATL_A0_TXD_SIZE 16U 23 #define HW_ATL_A0_RXD_SIZE 16U 24 25 #define HW_ATL_A0_MAC 0U 26 #define HW_ATL_A0_MAC_MIN 1U 27 #define HW_ATL_A0_MAC_MAX 33U 28 29 /* interrupts */ 30 #define HW_ATL_A0_ERR_INT 8U 31 #define HW_ATL_A0_INT_MASK 0xFFFFFFFFU 32 33 #define HW_ATL_A0_TXD_CTL2_LEN 0xFFFFC000U 34 #define HW_ATL_A0_TXD_CTL2_CTX_EN 0x00002000U 35 #define HW_ATL_A0_TXD_CTL2_CTX_IDX 0x00001000U 36 37 #define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD 0x00000001U 38 #define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC 0x00000002U 39 #define HW_ATL_A0_TXD_CTL_BLEN 0x000FFFF0U 40 #define HW_ATL_A0_TXD_CTL_DD 0x00100000U 41 #define HW_ATL_A0_TXD_CTL_EOP 0x00200000U 42 43 #define HW_ATL_A0_TXD_CTL_CMD_X 0x3FC00000U 44 45 #define HW_ATL_A0_TXD_CTL_CMD_VLAN BIT(22) 46 #define HW_ATL_A0_TXD_CTL_CMD_FCS BIT(23) 47 #define HW_ATL_A0_TXD_CTL_CMD_IPCSO BIT(24) 48 #define HW_ATL_A0_TXD_CTL_CMD_TUCSO BIT(25) 49 #define HW_ATL_A0_TXD_CTL_CMD_LSO BIT(26) 50 #define HW_ATL_A0_TXD_CTL_CMD_WB BIT(27) 51 #define HW_ATL_A0_TXD_CTL_CMD_VXLAN BIT(28) 52 53 #define HW_ATL_A0_TXD_CTL_CMD_IPV6 BIT(21) 54 #define HW_ATL_A0_TXD_CTL_CMD_TCP BIT(22) 55 56 #define HW_ATL_A0_MPI_CONTROL_ADR 0x0368U 57 #define HW_ATL_A0_MPI_STATE_ADR 0x036CU 58 59 #define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU 60 #define HW_ATL_A0_MPI_SPEED_SHIFT 16U 61 62 #define HW_ATL_A0_TXBUF_MAX 160U 63 #define HW_ATL_A0_RXBUF_MAX 320U 64 65 #define HW_ATL_A0_RSS_REDIRECTION_MAX 64U 66 #define HW_ATL_A0_RSS_REDIRECTION_BITS 3U 67 68 #define HW_ATL_A0_TC_MAX 1U 69 #define HW_ATL_A0_RSS_MAX 8U 70 71 #define HW_ATL_A0_FW_SEMA_RAM 0x2U 72 73 #define HW_ATL_A0_RXD_DD 0x1U 74 #define HW_ATL_A0_RXD_NCEA0 0x1U 75 76 #define HW_ATL_A0_RXD_WB_STAT2_EOP 0x0002U 77 78 #define HW_ATL_A0_UCP_0X370_REG 0x370U 79 80 #define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U 81 82 #define HW_ATL_A0_MIN_RXD \ 83 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) 84 #define HW_ATL_A0_MIN_TXD \ 85 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE)) 86 87 #define HW_ATL_A0_MAX_RXD 8184U 88 #define HW_ATL_A0_MAX_TXD 8184U 89 90 #endif /* HW_ATL_A0_INTERNAL_H */ 91