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Searched refs:I915_NUM_ENGINES (Results 1 – 23 of 23) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/gvt/
A Dscheduler.h47 struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
52 struct intel_vgpu *engine_owner[I915_NUM_ENGINES];
55 struct task_struct *thread[I915_NUM_ENGINES];
56 wait_queue_head_t waitq[I915_NUM_ENGINES];
A Dgvt.h150 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
151 struct list_head workload_q_head[I915_NUM_ENGINES];
152 struct intel_context *shadow[I915_NUM_ENGINES];
159 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
160 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
161 void *ring_scan_buffer[I915_NUM_ENGINES];
162 int ring_scan_buffer_size[I915_NUM_ENGINES];
170 } last_ctx[I915_NUM_ENGINES];
208 u32 hws_pga[I915_NUM_ENGINES];
341 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
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A Dvgpu.c280 for (i = 0; i < I915_NUM_ENGINES; i++) in intel_gvt_create_idle_vgpu()
A Dmmio_context.c154 u32 control_table[I915_NUM_ENGINES][GEN9_MOCS_SIZE];
A Dscheduler.c1420 bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES); in intel_vgpu_setup_submission()
1435 bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES); in intel_vgpu_setup_submission()
A Dcmd_parser.c596 static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
/linux-6.3-rc2/drivers/gpu/drm/i915/selftests/
A Digt_live_test.h20 unsigned int reset_engine[I915_NUM_ENGINES];
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_gt_types.h202 struct intel_engine_cs *engine[I915_NUM_ENGINES];
A Dintel_engine_types.h140 I915_NUM_ENGINES enumerator
A Dselftest_timeline.c284 return i915_prandom_u32_max_state(I915_NUM_ENGINES, rnd); in random_engine()
539 timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES, in live_hwsp_engine()
614 timelines = kvmalloc_array(NUM_TIMELINES * I915_NUM_ENGINES, in live_hwsp_alternate()
A Dmock_engine.c347 GEM_BUG_ON(id >= I915_NUM_ENGINES); in mock_engine()
A Dintel_engine_cs.c478 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES); in intel_engine_setup()
978 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES)); in intel_engines_init_mmio()
1565 static const i915_reg_t _reg[I915_NUM_ENGINES] = { in __cs_pending_mi_force_wakes()
A Dselftest_hangcheck.c989 threads = kmalloc_array(I915_NUM_ENGINES, sizeof(*threads), GFP_KERNEL); in __igt_reset_engines()
1012 memset(threads, 0, sizeof(*threads) * I915_NUM_ENGINES); in __igt_reset_engines()
A Dintel_gt.c513 struct i915_request *requests[I915_NUM_ENGINES] = {}; in __engines_record_defaults()
A Dselftest_workarounds.c34 } engine[I915_NUM_ENGINES];
A Dintel_reset.c1485 BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES > in intel_gt_set_wedged_on_init()
A Dselftest_execlists.c3553 struct kthread_worker *worker[I915_NUM_ENGINES] = {}; in smoke_crescendo()
3560 arg = kmalloc_array(I915_NUM_ENGINES, sizeof(*arg), GFP_KERNEL); in smoke_crescendo()
3564 memset(arg, 0, I915_NUM_ENGINES * sizeof(*arg)); in smoke_crescendo()
A Dintel_execlists_submission.c194 } nodes[I915_NUM_ENGINES];
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_gpu_error.h231 atomic_t reset_engine_count[I915_NUM_ENGINES];
A Dintel_device_info.c407 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); in intel_device_info_runtime_init()
A Di915_drv.h386 (id__) < I915_NUM_ENGINES; \
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc.h181 u32 ads_regset_count[I915_NUM_ENGINES];
/linux-6.3-rc2/drivers/gpu/drm/i915/gem/
A Di915_gem_context.c1099 const unsigned int max = I915_NUM_ENGINES; in default_engines()

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