Searched refs:ICL_PORT_DPLL_DEFAULT (Results 1 – 3 of 3) sorted by relevance
179 ICL_PORT_DPLL_DEFAULT, enumerator
3154 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; in icl_update_active_dpll()3175 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_combo_phy_dpll()3191 icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT); in icl_compute_combo_phy_dpll()3207 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_combo_phy_dpll()3265 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()3269 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_compute_tc_phy_dplls()3298 &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()3302 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()3330 port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; in icl_get_tc_phy_dplls()3381 for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) { in icl_put_dplls()
3508 enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; in intel_ddi_get_clock()3575 port_dpll_id = ICL_PORT_DPLL_DEFAULT; in icl_ddi_tc_get_clock()
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