Searched refs:IMX6SX_CLK_PLL5_POST_DIV (Results 1 – 2 of 2) sorted by relevance
42 #define IMX6SX_CLK_PLL5_POST_DIV 33 macro
251 hws[IMX6SX_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", in imx6sx_clocks_init()
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