Searched refs:IMX7ULP_CLK_DDR_DIV (Results 1 – 4 of 4) sorted by relevance
45 #define IMX7ULP_CLK_DDR_DIV 32 macro
97 <&scg1 IMX7ULP_CLK_DDR_DIV>,
272 <&scg1 IMX7ULP_CLK_DDR_DIV>,304 <&scg1 IMX7ULP_CLK_DDR_DIV>,
115 …hws[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK… in imx7ulp_clk_scg1_init()
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