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Searched refs:IMX7ULP_CLK_SOSC_BUS_CLK (Results 1 – 5 of 5) sorted by relevance

/linux-6.3-rc2/arch/arm/boot/dts/
A Dimx7ulp.dtsi155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
277 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
286 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
309 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
/linux-6.3-rc2/include/dt-bindings/clock/
A Dimx7ulp-clock.h55 #define IMX7ULP_CLK_SOSC_BUS_CLK 41 macro
/linux-6.3-rc2/Documentation/devicetree/bindings/pwm/
A Dimx-tpm-pwm.yaml54 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/
A Dimx7ulp-pcc-clock.yaml102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
/linux-6.3-rc2/drivers/clk/imx/
A Dclk-imx7ulp.c124 …hws[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_hw_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8… in imx7ulp_clk_scg1_init()

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