Searched refs:IMX93_CLK_SYS_PLL_PFD1_DIV2 (Results 1 – 3 of 3) sorted by relevance
234 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;431 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;594 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,619 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,621 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
15 #define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 macro
282 clks[IMX93_CLK_SYS_PLL_PFD1_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd1_div2", in imx93_clocks_probe()
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