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Searched refs:INVALIDATE_ALL_L1_TLBS (Results 1 – 25 of 25) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dgfxhub_v1_0.c189 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v1_0_init_cache_regs()
A Dgfxhub_v2_0.c228 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v2_0_init_cache_regs()
A Dgfxhub_v3_0_3.c235 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v3_0_3_init_cache_regs()
A Dgfxhub_v3_0.c230 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v3_0_init_cache_regs()
A Dmmhub_v3_0_2.c248 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v3_0_2_init_cache_regs()
A Dmmhub_v3_0_1.c249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v3_0_1_init_cache_regs()
A Dmmhub_v2_0.c299 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v2_0_init_cache_regs()
A Dmmhub_v2_3.c223 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v2_3_init_cache_regs()
A Dmmhub_v3_0.c256 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v3_0_init_cache_regs()
A Dmmhub_v1_0.c175 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_0_init_cache_regs()
A Dgfxhub_v2_1.c231 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gfxhub_v2_1_init_cache_regs()
A Dgmc_v7_0.c636 tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v7_0_gart_enable()
A Dmmhub_v1_7.c195 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v1_7_init_cache_regs()
A Dgmc_v8_0.c860 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); in gmc_v8_0_gart_enable()
A Dsid.h380 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
A Dmmhub_v9_4.c227 INVALIDATE_ALL_L1_TLBS, 1); in mmhub_v9_4_init_cache_regs()
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Drv770d.h648 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
A Dnid.h118 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
A Dsid.h379 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
A Dcikd.h497 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
A Devergreend.h1156 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
A Dni.c1287 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
A Dr600d.h593 #define INVALIDATE_ALL_L1_TLBS (1 << 0) macro
A Dsi.c4306 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
A Dcik.c5445 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()

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