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Searched refs:INVALIDATE_L2_CACHE (Results 1 – 25 of 25) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dgfxhub_v1_0.c190 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
A Dgfxhub_v2_0.c229 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
A Dgfxhub_v3_0_3.c236 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v3_0_3_init_cache_regs()
A Dgfxhub_v3_0.c231 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v3_0_init_cache_regs()
A Dmmhub_v3_0_2.c249 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_2_init_cache_regs()
A Dmmhub_v3_0_1.c250 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_1_init_cache_regs()
A Dmmhub_v2_0.c300 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v2_0_init_cache_regs()
A Dmmhub_v2_3.c224 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v2_3_init_cache_regs()
A Dmmhub_v3_0.c257 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v3_0_init_cache_regs()
A Dmmhub_v1_0.c176 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
A Dgfxhub_v2_1.c232 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gfxhub_v2_1_init_cache_regs()
A Dgmc_v7_0.c637 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
A Dmmhub_v1_7.c196 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in mmhub_v1_7_init_cache_regs()
A Dgmc_v8_0.c861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
A Dsid.h381 #define INVALIDATE_L2_CACHE (1 << 1) macro
A Dmmhub_v9_4.c229 INVALIDATE_L2_CACHE, 1); in mmhub_v9_4_init_cache_regs()
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Drv770d.h649 #define INVALIDATE_L2_CACHE (1 << 1) macro
A Dnid.h119 #define INVALIDATE_L2_CACHE (1 << 1) macro
A Dsid.h380 #define INVALIDATE_L2_CACHE (1 << 1) macro
A Dcikd.h498 #define INVALIDATE_L2_CACHE (1 << 1) macro
A Devergreend.h1157 #define INVALIDATE_L2_CACHE (1 << 1) macro
A Dni.c1287 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cayman_pcie_gart_enable()
A Dr600d.h594 #define INVALIDATE_L2_CACHE (1 << 1) macro
A Dsi.c4306 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
A Dcik.c5445 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()

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