| /linux-6.3-rc2/drivers/gpu/drm/i915/display/ |
| A D | intel_pps.c | 28 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_name()
346 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_num_pps()
395 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in pps_initial_setup()
485 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pps_get_registers()
531 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_power()
544 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in edp_have_panel_vdd()
1510 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in pps_init_registers()
1571 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_encoder_reset()
1610 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in pps_init_late()
1670 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_pps_setup()
[all …]
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| A D | g4x_dp.c | 71 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_set_clock()
467 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_link_down()
652 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_enable_dp()
662 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_enable_dp()
1264 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_dp_encoder_reset()
1321 } else if (IS_VALLEYVIEW(dev_priv)) { in g4x_dp_init()
1342 else if (IS_VALLEYVIEW(dev_priv)) in g4x_dp_init()
1351 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || in g4x_dp_init()
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| A D | intel_pipe_crc.c | 408 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in get_new_crc_ctl_reg()
538 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_is_valid_crc_source()
614 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_set_crc_source()
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| A D | intel_dsi_vbt.c | 494 else if (IS_VALLEYVIEW(dev_priv)) in mipi_exec_gpio()
979 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_init()
985 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_init()
1040 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_dsi_vbt_gpio_cleanup()
1044 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { in intel_dsi_vbt_gpio_cleanup()
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| A D | intel_vga.c | 20 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_vga_cntrl_reg()
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| A D | intel_cdclk.c | 488 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
500 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
535 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
2415 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2424 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
3022 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
3054 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3192 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3384 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
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| A D | intel_crt.c | 358 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_mode_valid()
571 if (IS_VALLEYVIEW(dev_priv)) in intel_crt_detect_hotplug()
993 else if (IS_VALLEYVIEW(dev_priv)) in intel_crt_init()
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| A D | intel_crtc.c | 341 IS_VALLEYVIEW(dev_priv) || IS_G4X(dev_priv)) in intel_crtc_init()
484 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_pipe_update_start()
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| A D | i9xx_plane.c | 805 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
839 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_primary_plane_create()
870 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in intel_primary_plane_create()
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| A D | intel_lpe_audio.c | 187 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { in lpe_audio_detect()
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| A D | intel_drrs.c | 73 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_drrs_set_refresh_rate_pipeconf()
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| A D | intel_display_debugfs.c | 98 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i915_sr_status()
1293 else if (IS_VALLEYVIEW(dev_priv)) in wm_latency_show()
1310 IS_VALLEYVIEW(dev_priv) || in wm_latency_show()
1412 else if (IS_VALLEYVIEW(dev_priv)) in wm_latency_write()
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| A D | intel_display.c | 275 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) in intel_update_czclk()
2358 else if (IS_VALLEYVIEW(dev_priv)) in i9xx_crtc_disable()
2999 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_set_pipeconf()
3205 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in i9xx_get_pipe_config()
3284 else if (IS_VALLEYVIEW(dev_priv)) in i9xx_get_pipe_config()
4922 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in compute_baseline_pipe_bpp()
5155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_crtc_prepare_cleared_state()
5499 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in fastboot_enabled()
5738 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_pipe_config_compare()
6152 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) || in active_planes_affects_min_cdclk()
[all …]
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| /linux-6.3-rc2/drivers/gpu/drm/i915/ |
| A D | vlv_sideband.c | 46 if (IS_VALLEYVIEW(i915)) { in __vlv_punit_get()
54 if (IS_VALLEYVIEW(i915)) in __vlv_punit_put()
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| A D | vlv_suspend.c | 386 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_suspend_complete()
431 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in vlv_resume_prepare()
461 if (!IS_VALLEYVIEW(i915)) in vlv_suspend_init()
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| A D | i915_irq.c | 190 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
1180 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_ack()
1219 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in i9xx_hpd_irq_handler()
1234 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in i9xx_hpd_irq_handler()
3948 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_irq_init()
3991 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_handler()
4016 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_reset()
4041 else if (IS_VALLEYVIEW(dev_priv)) in intel_irq_postinstall()
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| /linux-6.3-rc2/drivers/gpu/drm/i915/selftests/ |
| A D | intel_uncore.c | 175 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in live_forcewake_ops()
286 !IS_VALLEYVIEW(gt->i915) && in live_forcewake_domains()
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| /linux-6.3-rc2/drivers/gpu/drm/i915/gt/ |
| A D | intel_rc6.c | 586 else if (IS_VALLEYVIEW(i915)) in intel_rc6_init()
624 else if (IS_VALLEYVIEW(i915)) in intel_rc6_enable()
777 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_rc6_residency_ns()
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| A D | selftest_rc6.c | 51 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in live_rc6_manual()
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| A D | intel_rps.c | 704 if (IS_VALLEYVIEW(gt->i915)) in rps_set_power()
838 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in rps_set()
1541 else if (IS_VALLEYVIEW(i915)) in intel_rps_enable()
1639 else if (IS_VALLEYVIEW(i915)) in intel_gpu_freq()
1656 else if (IS_VALLEYVIEW(i915)) in intel_freq_opcode()
2016 else if (IS_VALLEYVIEW(i915)) in intel_rps_init()
2107 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_rps_get_cagf()
2135 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in read_cagf()
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| A D | intel_gt_pm_debugfs.c | 324 else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in drpc_show()
355 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { in intel_gt_pm_frequency_dump()
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| A D | intel_ggtt_fencing.c | 578 if (GRAPHICS_VER(i915) >= 8 || IS_VALLEYVIEW(i915)) { in detect_bit_6_swizzle()
853 !(IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))) in intel_ggtt_init_fences()
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| A D | intel_gt_sysfs_pm.c | 320 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) { in intel_sysfs_rc6_init()
723 if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) in intel_sysfs_rps_init()
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| A D | gen7_renderclear.c | 402 ((IS_IVB_GT1(i915) || IS_VALLEYVIEW(i915)) ? in emit_batch()
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| /linux-6.3-rc2/drivers/gpu/drm/i915/soc/ |
| A D | intel_gmch.c | 87 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_gmch_bar_setup()
|