| /linux-6.3-rc2/Documentation/devicetree/bindings/display/bridge/ |
| A D | renesas,lvds.yaml | 7 title: Renesas R-Car LVDS Encoder
19 - renesas,r8a7742-lvds # for RZ/G1H compatible LVDS encoders
20 - renesas,r8a7743-lvds # for RZ/G1M compatible LVDS encoders
21 - renesas,r8a7744-lvds # for RZ/G1N compatible LVDS encoders
22 - renesas,r8a774a1-lvds # for RZ/G2M compatible LVDS encoders
23 - renesas,r8a774b1-lvds # for RZ/G2N compatible LVDS encoders
24 - renesas,r8a774c0-lvds # for RZ/G2E compatible LVDS encoders
25 - renesas,r8a774e1-lvds # for RZ/G2H compatible LVDS encoders
26 - renesas,r8a7790-lvds # for R-Car H2 compatible LVDS encoders
62 description: LVDS output port
[all …]
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| A D | lvds-codec.yaml | 7 title: Transparent LVDS encoders and decoders
13 This binding supports transparent LVDS encoders and decoders that don't
18 to LVDS panels. This binding targets devices compatible with the following
23 [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
42 - ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
43 - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
46 - thine,thc63lvdm83d # For the THC63LVDM83D LVDS serializer
56 For LVDS encoders, port 0 is the parallel input
57 For LVDS decoders, port 0 is the LVDS input
77 For LVDS encoders, port 1 is the LVDS output
[all …]
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| A D | lontium,lt9211.yaml | 7 title: Lontium LT9211 DSI/LVDS/DPI to DSI/LVDS/DPI bridge.
13 The LT9211 are bridge devices which convert Single/Dual-Link DSI/LVDS
14 or Single DPI to Single/Dual-Link DSI/LVDS or Single DPI.
42 LVDS port-1 for LVDS input or DPI input.
47 Additional MIPI port-2 for MIPI input or LVDS port-2
48 for LVDS input. Used in combination with primary
55 LVDS port-1 for LVDS output or DPI output.
60 Additional MIPI port-2 for MIPI output or LVDS port-2
61 for LVDS output. Used in combination with primary
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| A D | toshiba,tc358775.yaml | 7 title: Toshiba TC358775 DSI to LVDS bridge
13 This binding supports DSI to LVDS bridge TC358775
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
18 limited by 135 MHz LVDS speed
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
20 panel, limited by 270 MHz LVDS speed.
31 description: 1.2V LVDS Power Supply
57 Video port for LVDS output (panel or connector).
62 Video port for Dual link LVDS output (panel or connector).
83 /* For single-link LVDS display panel */
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| A D | thine,thc63lvd1024.yaml | 7 title: Thine Electronics THC63LVD1024 LVDS Decoder
14 The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS
16 modes, handling up to two LVDS input streams and up to two digital CMOS/TTL
45 description: First LVDS input port
49 description: Second LVDS input port
73 Power supply for the TTL output, TTL CLOCKOUT signal, LVDS input, PLL and
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| A D | ti,sn65dsi83.yaml | 7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
14 to 1x Single-link LVDS
17 to 1x Dual-link or 2x Single-link LVDS
84 description: Video port for LVDS Channel-A output (panel or bridge).
88 description: Video port for LVDS Channel-B output (panel or bridge).
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| A D | fsl,ldb.yaml | 7 title: Freescale i.MX8MP DPI to LVDS bridge chip
14 for configuring the on-SoC DPI-to-LVDS serializer. This describes
47 description: Video port for LVDS Channel-A output (panel or bridge).
51 description: Video port for LVDS Channel-B output (panel or bridge).
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| A D | fsl,imx8qxp-pxl2dpi.yaml | 15 MIPI-DPI 24-bit data input, and inputs of LVDS Display Bridge(LDB) module
16 used in LVDS mode, to remap the pixel color codings between those modules.
38 LVDS Display Bridge(LDB) in split mode.
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| A D | toshiba,tc358764.txt | 1 TC358764 MIPI-DSI to LVDS panel bridge
14 1: LVDS Output, mandatory
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| A D | fsl,imx8qxp-ldb.yaml | 7 title: Freescale i.MX8qm/qxp LVDS Display Bridge
13 The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
23 LDB split mode to support a dual link LVDS display. The channel indexes
85 description: A phandle to the phy module representing the LVDS PHY.
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| /linux-6.3-rc2/Documentation/devicetree/bindings/phy/ |
| A D | fsl,imx8qm-lvds-phy.yaml | 7 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
13 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
15 groups of four data lanes of LVDS data streams. A phase-locked
17 data streams over a fifth LVDS link. Every cycle of the transmit
19 through the two groups of LVDS data streams. Together with the
20 transmit clocks, the two groups of LVDS data streams form two
21 LVDS channels.
23 The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
36 Cell allows setting the LVDS channel index of the PHY.
37 Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
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| /linux-6.3-rc2/Documentation/devicetree/bindings/display/imx/ |
| A D | ldb.txt | 1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
7 nodes describing each of the two LVDS encoder channels of the bridge.
15 interfaces as input for each LVDS channel.
23 "di0_pll" - LDB LVDS channel 0 mux
24 "di1_pll" - LDB LVDS channel 1 mux
25 "di0" - LDB LVDS channel 0 gate
26 "di1" - LDB LVDS channel 1 gate
44 LVDS Channel
59 to the four LVDS multiplexer inputs.
[all …]
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| /linux-6.3-rc2/Documentation/devicetree/bindings/display/ |
| A D | lvds.yaml | 7 title: LVDS Display Common Properties
14 LVDS is a physical layer specification defined in ANSI/TIA/EIA-644-A. Multiple
16 to LVDS devices. This bindings supports devices compatible with the following
21 [LDI] "Open LVDS Display Interface", May 1999 (Version 0.95), National
38 LVDS data mappings are defined as follows.
41 [VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
52 specifications. Data are transferred as follows on 4 LVDS lanes.
64 Data are transferred as follows on 4 LVDS lanes.
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| A D | renesas,du.yaml | 190 description: LVDS 0
354 description: LVDS 0
413 description: LVDS 0
415 description: LVDS 1
482 description: LVDS 0
551 description: LVDS 0
620 description: LVDS 0
677 description: LVDS 0
736 description: LVDS 0
738 description: LVDS 1
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| /linux-6.3-rc2/drivers/gpu/drm/bridge/ |
| A D | Kconfig | 74 Support for i.MX8MP DPI-to-LVDS on-SoC encoder.
108 tristate "Lontium LT9211 DSI/LVDS/DPI bridge"
172 GE B850v3 that convert dual channel LVDS
193 tristate "NXP PTN3460 DP/LVDS bridge"
198 NXP PTN3460 eDP-LVDS bridge chip driver.
201 tristate "Parade eDP/LVDS bridge"
207 Parade eDP-LVDS bridge chip driver.
274 tristate "TC358764 DSI/LVDS bridge"
280 Toshiba TC358764 DSI/LVDS bridge driver.
305 tristate "Toshiba TC358775 DSI/LVDS bridge"
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| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | imx7s-colibri-iris-v2.dts | 31 * This switches the LVDS transceiver to VESA color mapping mode.
43 * This switches the LVDS transceiver to the 24-bit RGB mode.
53 * This switches the LVDS transceiver to the single-channel
63 /* This turns the LVDS transceiver on */
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| A D | imx6ull-colibri-wifi-iris-v2.dts | 31 /* This turns the LVDS transceiver on */
42 * This switches the LVDS transceiver to the single-channel
53 * This switches the LVDS transceiver to the 24-bit RGB mode.
65 * This switches the LVDS transceiver to VESA color mapping mode.
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| A D | imx7d-colibri-iris-v2.dts | 31 * This switches the LVDS transceiver to VESA color mapping mode.
43 * This switches the LVDS transceiver to the 24-bit RGB mode.
53 * This switches the LVDS transceiver to the single-channel
63 /* This turns the LVDS transceiver on */
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| A D | imx6ull-colibri-iris-v2.dts | 31 /* This turns the LVDS transceiver on */
42 * This switches the LVDS transceiver to the single-channel
53 * This switches the LVDS transceiver to the 24-bit RGB mode.
65 * This switches the LVDS transceiver to VESA color mapping mode.
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| A D | tegra30-asus-lvds-display.dtsi | 3 /* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */
35 /* Texas Instruments SN75LVDS83B LVDS Transmitter */
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| /linux-6.3-rc2/arch/arm64/boot/dts/renesas/ |
| A D | r8a774c0-ek874-idk-2121wr.dts | 4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel
68 * When GP0_17 is low LVDS[01] are connected to the LVDS connector
69 * When GP0_17 is high LVDS[01] are connected to the LT8918L
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| A D | hihope-rzg2-ex-lvds.dtsi | 3 * Device Tree Source for the RZ/G2[MN] HiHope sub board LVDS common parts
20 * When GP1_20 is LOW LVDS0 is connected to the LVDS connector
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| /linux-6.3-rc2/drivers/gpu/drm/bridge/imx/ |
| A D | Kconfig | 4 tristate "Freescale i.MX8QM LVDS display bridge"
9 Choose this to enable the internal LVDS Display Bridge(LDB) found in
13 tristate "Freescale i.MX8QXP LVDS display bridge"
18 Choose this to enable the internal LVDS Display Bridge(LDB) found in
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| /linux-6.3-rc2/drivers/gpu/drm/rockchip/ |
| A D | Kconfig | 83 bool "Rockchip LVDS support"
87 Choose this option to enable support for Rockchip LVDS controllers.
88 Rockchip rk3288 SoC has LVDS TX Controller can be used, and it
89 support LVDS, rgb, dual LVDS output mode. say Y to enable its
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| /linux-6.3-rc2/Documentation/devicetree/bindings/display/panel/ |
| A D | advantech,idk-2121wr.yaml | 7 title: Advantech IDK-2121WR 21.5" Full-HD dual-LVDS panel
14 The IDK-2121WR from Advantech is a Full-HD dual-LVDS panel.
15 A dual-LVDS interface is a dual-link connection with even pixels traveling
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