Searched refs:M4U_LARB0_ID (Results 1 – 7 of 7) sorted by relevance
| /linux-6.3-rc2/include/dt-bindings/memory/ |
| A D | mt6795-larb-port.h | 12 #define M4U_LARB0_ID 0 macro
19 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
20 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
21 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 2)
22 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
23 #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4)
24 #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 5)
26 #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 7)
27 #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 8)
28 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 9)
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| A D | mediatek,mt8365-larb-port.h | 11 #define M4U_LARB0_ID 0 macro
17 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
18 #define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1)
19 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
20 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
21 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
22 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
23 #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6)
24 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
25 #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8)
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| A D | mt8167-larb-port.h | 13 #define M4U_LARB0_ID 0 macro
18 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
19 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
20 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
21 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3)
22 #define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4)
23 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5)
24 #define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6)
25 #define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7)
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| A D | mt2712-larb-port.h | 11 #define M4U_LARB0_ID 0 macro
23 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
24 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
25 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
26 #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
27 #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
28 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
29 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
30 #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7)
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| A D | mt8183-larb-port.h | 11 #define M4U_LARB0_ID 0 macro
21 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
22 #define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1)
23 #define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2)
24 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
25 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
26 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
27 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
28 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
29 #define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8)
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| A D | mt8173-larb-port.h | 11 #define M4U_LARB0_ID 0 macro
19 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
20 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
21 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
22 #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
23 #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
24 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
25 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
26 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
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| A D | mt6779-larb-port.h | 12 #define M4U_LARB0_ID 0 macro
26 #define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0)
27 #define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1)
28 #define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2)
29 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3)
30 #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4)
31 #define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5)
32 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
33 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7)
34 #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8)
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