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Searched refs:MDIO_MMD_VEND2 (Results 1 – 19 of 19) sorted by relevance

/linux-6.3-rc2/drivers/net/pcs/
A Dpcs-xpcs-nxp.c74 return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL2, in nxp_sja1105_sgmii_pma_config()
89 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL0, in nxp_sja1110_pma_config()
94 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_TXPLL_CTRL1, in nxp_sja1110_pma_config()
100 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER1_0, in nxp_sja1110_pma_config()
107 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DRIVER2_0, val); in nxp_sja1110_pma_config()
122 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_TRIM, val); in nxp_sja1110_pma_config()
127 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_LANE_DATAPATH_1, 0); in nxp_sja1110_pma_config()
134 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL0, in nxp_sja1110_pma_config()
139 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RXPLL_CTRL1, in nxp_sja1110_pma_config()
155 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE); in nxp_sja1110_pma_config()
[all …]
A Dpcs-xpcs.c254 dev = MDIO_MMD_VEND2; in xpcs_soft_reset()
400 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); in xpcs_config_usxgmii()
407 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); in xpcs_config_usxgmii()
827 ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2, in xpcs_config_aneg_c37_1000basex()
1015 lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA); in xpcs_get_state_c37_1000basex()
1019 bmsr = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_BMSR); in xpcs_get_state_c37_1000basex()
1077 ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val); in xpcs_link_up_sgmii()
1130 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1); in xpcs_an_restart()
1133 xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret); in xpcs_an_restart()
1160 ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_PHYSID1); in xpcs_get_id()
[all …]
A Dpcs-lynx.c52 status = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_BMSR); in lynx_pcs_get_state_usxgmii()
61 lpa = mdiobus_c45_read(bus, addr, MDIO_MMD_VEND2, MII_LPA); in lynx_pcs_get_state_usxgmii()
168 return mdiobus_c45_write(bus, addr, MDIO_MMD_VEND2, MII_ADVERTISE, in lynx_pcs_config_usxgmii()
/linux-6.3-rc2/drivers/net/ethernet/microchip/
A Dlan743x_ethtool.c1238 { ETH_SR_MII_CTRL, MDIO_MMD_VEND2, 0x0000}, in lan743x_sgmii_regs()
1239 { ETH_SR_MII_STS, MDIO_MMD_VEND2, 0x0001}, in lan743x_sgmii_regs()
1240 { ETH_SR_MII_DEV_ID1, MDIO_MMD_VEND2, 0x0002}, in lan743x_sgmii_regs()
1241 { ETH_SR_MII_DEV_ID2, MDIO_MMD_VEND2, 0x0003}, in lan743x_sgmii_regs()
1242 { ETH_SR_MII_AN_ADV, MDIO_MMD_VEND2, 0x0004}, in lan743x_sgmii_regs()
1243 { ETH_SR_MII_LP_BABL, MDIO_MMD_VEND2, 0x0005}, in lan743x_sgmii_regs()
1244 { ETH_SR_MII_EXPN, MDIO_MMD_VEND2, 0x0006}, in lan743x_sgmii_regs()
1245 { ETH_SR_MII_EXT_STS, MDIO_MMD_VEND2, 0x000F}, in lan743x_sgmii_regs()
1246 { ETH_SR_MII_TIME_SYNC_ABL, MDIO_MMD_VEND2, 0x0708}, in lan743x_sgmii_regs()
1247 { ETH_SR_MII_TIME_SYNC_TX_MAX_DLY_LWR, MDIO_MMD_VEND2, 0x0709}, in lan743x_sgmii_regs()
[all …]
A Dlan743x_main.c998 mpllctrl0 = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1014 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1019 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1024 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_mpll_set()
1044 ret = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_is_sgmii_2_5G_mode()
1084 dgt_ctrl = lan743x_sgmii_read(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_aneg_update()
1100 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_aneg_update()
1111 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, MII_BMCR, in lan743x_sgmii_aneg_update()
1116 ret = lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_aneg_update()
1121 return lan743x_sgmii_write(adapter, MDIO_MMD_VEND2, in lan743x_sgmii_aneg_update()
[all …]
/linux-6.3-rc2/drivers/net/phy/
A Ddp83td510.c57 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PHY_STS, in dp83td510_config_intr()
62 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
68 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
74 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
79 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
86 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PHY_STS, in dp83td510_config_intr()
97 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_PHY_STS); in dp83td510_handle_interrupt()
106 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_INTERRUPT_REG_1); in dp83td510_handle_interrupt()
153 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_read_status()
196 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TD510E_MSE_DETECT); in dp83td510_get_sqi()
A Dintel-xway.c255 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, in xway_gphy_config_init()
259 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, in xway_gphy_config_init()
272 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, ledxh); in xway_gphy_config_init()
273 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, ledxl); in xway_gphy_config_init()
274 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, ledxh); in xway_gphy_config_init()
275 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, ledxl); in xway_gphy_config_init()
276 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh); in xway_gphy_config_init()
277 phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl); in xway_gphy_config_init()
A Dmarvell10g.c188 return phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP); in mv3310_hwmon_read_temp_reg()
265 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP, in mv3310_hwmon_config()
272 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, MV_V2_TEMP_CTRL, in mv3310_hwmon_config()
1268 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MV_V2_WOL_CTRL); in mv3110_get_wol()
1283 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1290 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1297 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1304 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1312 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
1320 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
[all …]
A Dphy-c45.c1166 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1175 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1181 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1188 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1227 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1242 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1259 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1267 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1282 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1299 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
[all …]
A Dmarvell-88x2222.c81 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
86 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND2, MV_PORT_RST, in mv2222_soft_reset()
202 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
205 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
208 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MV_PCS_CONFIG, in mv2222_config_line()
A Dmxl-gpy.c684 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
691 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
698 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
711 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
725 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
761 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, VPSPEC2_WOL_CTL); in gpy_get_wol()
A Dncn26000.c45 return phy_write_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR, in ncn26000_config_init()
A Dphy_device.c793 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
831 if (i == MDIO_MMD_VEND1 || i == MDIO_MMD_VEND2) { in get_phy_c45_ids()
/linux-6.3-rc2/drivers/net/dsa/sja1105/
A Dsja1105_mdio.c20 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_read_c45()
23 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1105_pcs_mdio_read_c45()
25 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1105_pcs_mdio_read_c45()
46 if (mmd != MDIO_MMD_VEND1 && mmd != MDIO_MMD_VEND2) in sja1105_pcs_mdio_write_c45()
67 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID1) in sja1110_pcs_mdio_read_c45()
69 if (mmd == MDIO_MMD_VEND2 && (reg & GENMASK(15, 0)) == MII_PHYSID2) in sja1110_pcs_mdio_read_c45()
A Dsja1105_main.c2261 MDIO_MMD_VEND2, MDIO_CTRL1); in sja1105_static_config_reload()
/linux-6.3-rc2/drivers/net/ethernet/amd/xgbe/
A Dxgbe-mdio.c151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_clear_interrupts()
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg); in xgbe_an37_clear_interrupts()
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_disable_interrupts()
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_disable_interrupts()
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_enable_interrupts()
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg); in xgbe_an37_enable_interrupts()
368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1); in xgbe_an37_set()
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); in xgbe_an37_set()
663 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT); in xgbe_an37_isr()
985 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL); in xgbe_an37_init()
[all …]
A Dxgbe-phy-v2.c1659 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE); in xgbe_phy_an37_outcome()
1660 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY); in xgbe_phy_an37_outcome()
/linux-6.3-rc2/include/uapi/linux/
A Dmdio.h28 #define MDIO_MMD_VEND2 31 /* Vendor specific 2 */ macro
155 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
/linux-6.3-rc2/drivers/net/dsa/
A Dmt7530.c151 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); in core_write()
164 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); in core_rmw()
167 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); in core_rmw()
2382 MDIO_MMD_VEND2, CORE_PLL_GROUP4); in mt7531_setup()
2385 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, in mt7531_setup()

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