1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022 MediaTek Inc.
4  * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
5  */
6 
7 #ifndef __MTK_MDP3_COMP_H__
8 #define __MTK_MDP3_COMP_H__
9 
10 #include "mtk-mdp3-cmdq.h"
11 
12 #define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask, ...)	\
13 	cmdq_pkt_write_mask(&((cmd)->pkt), id,			\
14 		(base) + (ofst), (val), (mask), ##__VA_ARGS__)
15 
16 #define MM_REG_WRITE(cmd, id, base, ofst, val, mask, ...)	\
17 do {								\
18 	typeof(mask) (m) = (mask);				\
19 	MM_REG_WRITE_MASK(cmd, id, base, ofst, val,		\
20 		(((m) & (ofst##_MASK)) == (ofst##_MASK)) ?	\
21 			(0xffffffff) : (m), ##__VA_ARGS__);	\
22 } while (0)
23 
24 #define MM_REG_WAIT(cmd, evt)					\
25 do {								\
26 	typeof(cmd) (c) = (cmd);				\
27 	typeof(evt) (e) = (evt);				\
28 	cmdq_pkt_wfe(&((c)->pkt), (e), true);			\
29 } while (0)
30 
31 #define MM_REG_WAIT_NO_CLEAR(cmd, evt)				\
32 do {								\
33 	typeof(cmd) (c) = (cmd);				\
34 	typeof(evt) (e) = (evt);				\
35 	cmdq_pkt_wfe(&((c)->pkt), (e), false);			\
36 } while (0)
37 
38 #define MM_REG_CLEAR(cmd, evt)					\
39 do {								\
40 	typeof(cmd) (c) = (cmd);				\
41 	typeof(evt) (e) = (evt);				\
42 	cmdq_pkt_clear_event(&((c)->pkt), (e));			\
43 } while (0)
44 
45 #define MM_REG_SET_EVENT(cmd, evt)				\
46 do {								\
47 	typeof(cmd) (c) = (cmd);				\
48 	typeof(evt) (e) = (evt);				\
49 	cmdq_pkt_set_event(&((c)->pkt), (e));			\
50 } while (0)
51 
52 #define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask, ...)	\
53 do {								\
54 	typeof(_mask) (_m) = (_mask);				\
55 	cmdq_pkt_poll_mask(&((cmd)->pkt), id,			\
56 		(base) + (ofst), (val), (_m), ##__VA_ARGS__);	\
57 } while (0)
58 
59 #define MM_REG_POLL(cmd, id, base, ofst, val, mask, ...)	\
60 do {								\
61 	typeof(mask) (m) = (mask);				\
62 	MM_REG_POLL_MASK((cmd), id, base, ofst, val,		\
63 		(((m) & (ofst##_MASK)) == (ofst##_MASK)) ?	\
64 			(0xffffffff) : (m), ##__VA_ARGS__);	\
65 } while (0)
66 
67 enum mtk_mdp_comp_id {
68 	MDP_COMP_NONE = -1,	/* Invalid engine */
69 
70 	/* ISP */
71 	MDP_COMP_WPEI = 0,
72 	MDP_COMP_WPEO,		/* 1 */
73 	MDP_COMP_WPEI2,		/* 2 */
74 	MDP_COMP_WPEO2,		/* 3 */
75 	MDP_COMP_ISP_IMGI,	/* 4 */
76 	MDP_COMP_ISP_IMGO,	/* 5 */
77 	MDP_COMP_ISP_IMG2O,	/* 6 */
78 
79 	/* IPU */
80 	MDP_COMP_IPUI,		/* 7 */
81 	MDP_COMP_IPUO,		/* 8 */
82 
83 	/* MDP */
84 	MDP_COMP_CAMIN,		/* 9 */
85 	MDP_COMP_CAMIN2,	/* 10 */
86 	MDP_COMP_RDMA0,		/* 11 */
87 	MDP_COMP_AAL0,		/* 12 */
88 	MDP_COMP_CCORR0,	/* 13 */
89 	MDP_COMP_RSZ0,		/* 14 */
90 	MDP_COMP_RSZ1,		/* 15 */
91 	MDP_COMP_TDSHP0,	/* 16 */
92 	MDP_COMP_COLOR0,	/* 17 */
93 	MDP_COMP_PATH0_SOUT,	/* 18 */
94 	MDP_COMP_PATH1_SOUT,	/* 19 */
95 	MDP_COMP_WROT0,		/* 20 */
96 	MDP_COMP_WDMA,		/* 21 */
97 
98 	/* Dummy Engine */
99 	MDP_COMP_RDMA1,		/* 22 */
100 	MDP_COMP_RSZ2,		/* 23 */
101 	MDP_COMP_TDSHP1,	/* 24 */
102 	MDP_COMP_WROT1,		/* 25 */
103 
104 	MDP_MAX_COMP_COUNT	/* ALWAYS keep at the end */
105 };
106 
107 enum mdp_comp_type {
108 	MDP_COMP_TYPE_INVALID = 0,
109 
110 	MDP_COMP_TYPE_RDMA,
111 	MDP_COMP_TYPE_RSZ,
112 	MDP_COMP_TYPE_WROT,
113 	MDP_COMP_TYPE_WDMA,
114 	MDP_COMP_TYPE_PATH,
115 
116 	MDP_COMP_TYPE_TDSHP,
117 	MDP_COMP_TYPE_COLOR,
118 	MDP_COMP_TYPE_DRE,
119 	MDP_COMP_TYPE_CCORR,
120 	MDP_COMP_TYPE_HDR,
121 
122 	MDP_COMP_TYPE_IMGI,
123 	MDP_COMP_TYPE_WPEI,
124 	MDP_COMP_TYPE_EXTO,	/* External path */
125 	MDP_COMP_TYPE_DL_PATH,	/* Direct-link path */
126 
127 	MDP_COMP_TYPE_COUNT	/* ALWAYS keep at the end */
128 };
129 
130 #define MDP_GCE_NO_EVENT (-1)
131 enum {
132 	MDP_GCE_EVENT_SOF = 0,
133 	MDP_GCE_EVENT_EOF = 1,
134 	MDP_GCE_EVENT_MAX,
135 };
136 
137 struct mdp_comp_ops;
138 
139 struct mdp_comp {
140 	struct mdp_dev			*mdp_dev;
141 	void __iomem			*regs;
142 	phys_addr_t			reg_base;
143 	u8				subsys_id;
144 	struct clk			*clks[6];
145 	struct device			*comp_dev;
146 	enum mdp_comp_type		type;
147 	enum mtk_mdp_comp_id		id;
148 	u32				alias_id;
149 	s32				gce_event[MDP_GCE_EVENT_MAX];
150 	const struct mdp_comp_ops	*ops;
151 };
152 
153 struct mdp_comp_ctx {
154 	struct mdp_comp			*comp;
155 	const struct img_compparam	*param;
156 	const struct img_input		*input;
157 	const struct img_output		*outputs[IMG_MAX_HW_OUTPUTS];
158 };
159 
160 struct mdp_comp_ops {
161 	s64 (*get_comp_flag)(const struct mdp_comp_ctx *ctx);
162 	int (*init_comp)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd);
163 	int (*config_frame)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd,
164 			    const struct v4l2_rect *compose);
165 	int (*config_subfrm)(struct mdp_comp_ctx *ctx,
166 			     struct mdp_cmdq_cmd *cmd, u32 index);
167 	int (*wait_comp_event)(struct mdp_comp_ctx *ctx,
168 			       struct mdp_cmdq_cmd *cmd);
169 	int (*advance_subfrm)(struct mdp_comp_ctx *ctx,
170 			      struct mdp_cmdq_cmd *cmd, u32 index);
171 	int (*post_process)(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd);
172 };
173 
174 struct mdp_dev;
175 
176 int mdp_comp_config(struct mdp_dev *mdp);
177 void mdp_comp_destroy(struct mdp_dev *mdp);
178 int mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp);
179 void mdp_comp_clock_off(struct device *dev, struct mdp_comp *comp);
180 int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num);
181 void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num);
182 int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
183 			const struct img_compparam *param,
184 			const struct img_ipi_frameparam *frame);
185 
186 #endif  /* __MTK_MDP3_COMP_H__ */
187