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Searched refs:MISC (Results 1 – 25 of 30) sorted by relevance

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/linux-6.3-rc2/Documentation/devicetree/bindings/mfd/
A Dbrcm,misc.yaml7 title: Broadcom's MISC block
13 Broadcom's MISC is a hardware block used on some SoCs (e.g. bcm63xx and
24 description: MISC block registers
/linux-6.3-rc2/drivers/infiniband/hw/hfi1/
A Dchip_registers.h12 #define MISC (CORE + 0x000000500000) macro
558 #define MISC_CFG_FW_CTRL (MISC + 0x000000001000)
562 #define MISC_CFG_RSA_CMD (MISC + 0x000000000A08)
563 #define MISC_CFG_RSA_MODULUS (MISC + 0x000000000400)
564 #define MISC_CFG_RSA_MU (MISC + 0x000000000A10)
565 #define MISC_CFG_RSA_R2 (MISC + 0x000000000000)
566 #define MISC_CFG_RSA_SIGNATURE (MISC + 0x000000000200)
567 #define MISC_CFG_SHA_PRELOAD (MISC + 0x000000000A00)
568 #define MISC_ERR_CLEAR (MISC + 0x000000002010)
569 #define MISC_ERR_MASK (MISC + 0x000000002008)
[all …]
/linux-6.3-rc2/Documentation/devicetree/bindings/reset/
A Dbrcm,bcm4908-misc-pcie-reset.yaml7 title: Broadcom MISC block PCIe reset controller
10 signals. On BCM4908 it's a part of the MISC block.
/linux-6.3-rc2/Documentation/devicetree/bindings/misc/
A Dnvidia,tegra186-misc.yaml7 title: NVIDIA Tegra186 (and later) MISC register block
13 description: The MISC register block found on Tegra186 and later SoCs contains
/linux-6.3-rc2/Documentation/devicetree/bindings/interrupt-controller/
A Dqca,ath79-misc-intc.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
/linux-6.3-rc2/drivers/mfd/
A Dmt6358-irq.c30 MT6357_TOP_GEN(MISC),
41 MT6358_TOP_GEN(MISC),
52 MT6359_TOP_GEN(MISC),
/linux-6.3-rc2/Documentation/devicetree/bindings/phy/
A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
23 u2 port1 0x1000 MISC
26 u2 port2 0x2000 MISC
A Dmediatek,tphy.yaml39 u2 port0 0x0000 MISC
48 u2 port1 0x1000 MISC
57 u2 port2 0x2000 MISC
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
/linux-6.3-rc2/drivers/usb/misc/sisusbvga/
A Dsisusb_struct.h73 unsigned char MISC; member
/linux-6.3-rc2/drivers/pci/hotplug/
A Dcpqphp.h142 MISC = offsetof(struct ctrl_reg, misc), enumerator
474 misc = readw(ctrl->hpc_reg + MISC); in set_SOGO()
476 writew(misc, ctrl->hpc_reg + MISC); in set_SOGO()
603 misc = readw(ctrl->hpc_reg + MISC); in get_controller_speed()
A Dcpqphp_core.c1153 temp_word = readw(ctrl->hpc_reg + MISC); in cpqhpc_probe()
1155 writew(temp_word, ctrl->hpc_reg + MISC); in cpqhpc_probe()
1269 misc = readw(ctrl->hpc_reg + MISC); in unload_cpqphpd()
1271 writew(misc, ctrl->hpc_reg + MISC); in unload_cpqphpd()
A Dcpqphp_ctrl.c886 misc = readw(ctrl->hpc_reg + MISC); in cpqhp_ctrl_intr()
900 writew(misc, ctrl->hpc_reg + MISC); in cpqhp_ctrl_intr()
903 misc = readw(ctrl->hpc_reg + MISC); in cpqhp_ctrl_intr()
/linux-6.3-rc2/drivers/accel/ivpu/
A Divpu_hw_mtl.c96 ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n", in ivpu_hw_read_platform()
643 ivpu_dbg(vdev, MISC, "Tile Fuse: Enable Lower\n"); in ivpu_hw_mtl_info_init()
648 ivpu_dbg(vdev, MISC, "Tile Fuse: Enable Upper\n"); in ivpu_hw_mtl_info_init()
653 ivpu_dbg(vdev, MISC, "Tile Fuse: Enable Both\n"); in ivpu_hw_mtl_info_init()
657 ivpu_dbg(vdev, MISC, "Tile Fuse: Disable\n"); in ivpu_hw_mtl_info_init()
A Divpu_drv.c412 ivpu_dbg(vdev, MISC, "Mapping BAR0 (RegV) %pR\n", bar0); in ivpu_pci_init()
419 ivpu_dbg(vdev, MISC, "Mapping BAR4 (RegB) %pR\n", bar4); in ivpu_pci_init()
/linux-6.3-rc2/drivers/infiniband/sw/rdmavt/
A Dvt.c280 MISC, enumerator
383 case MISC: in check_support()
/linux-6.3-rc2/drivers/net/ethernet/realtek/
A Dr8169_main.c320 MISC = 0xf0, /* 8168e only. */ enumerator
2424 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); in rtl_disable_rxdvgate()
2429 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); in rtl_enable_rxdvgate()
2863 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); in rtl_hw_start_8168e_1()
2864 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); in rtl_hw_start_8168e_1()
2898 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168e_2()
2921 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); in rtl_hw_start_8168f()
3487 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); in rtl_hw_start_8106()
/linux-6.3-rc2/arch/m68k/ifpsp060/
A DREADME71 MISC Release file version numbers
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-s5pv210.c63 #define MISC 0xe000 macro
383 MUX(MOUT_CLKOUT, "mout_clkout", mout_clkout_p, MISC, 8, 2),
/linux-6.3-rc2/drivers/video/fbdev/sis/
A Dvstruct.h135 unsigned char MISC; member
/linux-6.3-rc2/Documentation/devicetree/bindings/net/
A Dti,cpsw-switch.yaml61 - description: MISC interrupt
/linux-6.3-rc2/arch/arm/boot/dts/
A Dvf610-bk4.dts352 /* MISC */
/linux-6.3-rc2/fs/
A DKconfig.binfmt146 tristate "Kernel support for MISC binaries"
/linux-6.3-rc2/Documentation/translations/zh_CN/loongarch/
A Dintroduction.rst101 0x3 杂项控制 MISC
/linux-6.3-rc2/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_init.h596 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1),
/linux-6.3-rc2/Documentation/firmware-guide/acpi/apei/
A Deinj.rst180 [22715.834759] EDAC sbridge MC3: ADDR 12345000 EDAC sbridge MC3: MISC 144780c86

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