Searched refs:MTL_VPU_HOST_SS_CPR_RST_CLR (Results 1 – 2 of 2) sorted by relevance
258 u32 val = REGV_RD32(MTL_VPU_HOST_SS_CPR_RST_CLR); in ivpu_boot_host_ss_rst_clr_assert()260 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in ivpu_boot_host_ss_rst_clr_assert()261 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in ivpu_boot_host_ss_rst_clr_assert()262 val = REG_SET_FLD(MTL_VPU_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in ivpu_boot_host_ss_rst_clr_assert()264 REGV_WR32(MTL_VPU_HOST_SS_CPR_RST_CLR, val); in ivpu_boot_host_ss_rst_clr_assert()
93 #define MTL_VPU_HOST_SS_CPR_RST_CLR 0x00000098u macro
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