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Searched refs:MTL_VPU_TOP_NOC_QREQN (Results 1 – 2 of 2) sorted by relevance

/linux-6.3-rc2/drivers/accel/ivpu/
A Divpu_hw_mtl.c333 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN); in ivpu_boot_top_noc_qrenqn_check()
335 if (!REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in ivpu_boot_top_noc_qrenqn_check()
336 !REG_TEST_FLD_NUM(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) in ivpu_boot_top_noc_qrenqn_check()
416 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN); in ivpu_boot_host_ss_top_noc_drive()
418 val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
419 val = REG_SET_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in ivpu_boot_host_ss_top_noc_drive()
421 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
422 val = REG_CLR_FLD(MTL_VPU_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in ivpu_boot_host_ss_top_noc_drive()
424 REGV_WR32(MTL_VPU_TOP_NOC_QREQN, val); in ivpu_boot_host_ss_top_noc_drive()
A Divpu_hw_mtl_reg.h115 #define MTL_VPU_TOP_NOC_QREQN 0x00000160u macro

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