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Searched refs:NUM_UCLK_DPM_LEVELS (Results 1 – 15 of 15) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/inc/
A Dsmu9_driver_if.h41 #define NUM_UCLK_DPM_LEVELS 4 macro
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
221 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */
222 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */
223 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
A Dsmu11_driver_if.h42 #define NUM_UCLK_DPM_LEVELS 4 macro
57 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
425 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
A Dsmu13_driver_if_v13_0_7.h43 #define NUM_UCLK_DPM_LEVELS 4 macro
1073 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1136 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz
1142 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
1143 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:…
1145 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1146 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1417 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1577 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16
1578 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];
[all …]
A Dsmu13_driver_if_v13_0_0.h40 #define NUM_UCLK_DPM_LEVELS 4 macro
1035 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1106 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
1107 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:…
1109 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1110 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1384 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1545 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16
1546 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];
1547 uint8_t Mem_DownHystLimit[NUM_UCLK_DPM_LEVELS];
A Dsmu11_driver_if_sienna_cichlid.h45 #define NUM_UCLK_DPM_LEVELS 4 macro
64 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
685 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
698 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, …
707 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
708 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
747 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
1045 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1067 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1068 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
[all …]
A Dsmu13_driver_if_aldebaran.h31 #define NUM_UCLK_DPM_LEVELS 4 macro
302 uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK
303 uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK
A Dsmu11_driver_if_navi10.h45 #define NUM_UCLK_DPM_LEVELS 4 macro
60 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
589 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
599 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, …
604 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
605 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
A Dsmu11_driver_if_arcturus.h39 #define NUM_UCLK_DPM_LEVELS 4 macro
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
519 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
A Dsmu9_driver_if.h40 #define NUM_UCLK_DPM_LEVELS 4 macro
53 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
313 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsienna_cichlid_ppt.c2686 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
2704 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
2719 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
2723 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
2769 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in beige_goby_dump_pptable()
3324 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
3342 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
3357 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
3361 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
3407 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()
A Darcturus_ppt.c1787 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega20_processpptables.c332 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
A Dvega10_hwmgr.c1890 while (i < NUM_UCLK_DPM_LEVELS) { in vega10_populate_all_memory_levels()
3614 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; in vega10_get_soc_index_for_max_uclk()
3640 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) in vega10_upload_dpm_bootup_level()
A Dvega12_hwmgr.c2518 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega12_set_uclk_to_highest_dpm_level()
A Dvega20_hwmgr.c3575 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega20_set_uclk_to_highest_dpm_level()

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