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Searched refs:OSC (Results 1 – 12 of 12) sorted by relevance

/linux-6.3-rc2/drivers/clk/loongson1/
A Dclk-loongson1c.c13 #define OSC (24 * 1000000) macro
25 rate *= OSC; in ls1x_pll_recalc_rate()
47 hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); in ls1x_clk_init()
A Dclk-loongson1b.c14 #define OSC (33 * 1000000) macro
26 rate *= OSC; in ls1x_pll_recalc_rate()
44 hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); in ls1x_clk_init()
/linux-6.3-rc2/drivers/clk/versatile/
A DKconfig23 tristate "Clock driver for Versatile Express OSC clock generators"
/linux-6.3-rc2/Documentation/devicetree/bindings/timer/
A Dnvidia,tegra186-timer.yaml15 reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
/linux-6.3-rc2/arch/arm/boot/dts/
A Dimx6ulz-bsh-smm-m2.dts147 MX6UL_PAD_ENET1_RX_EN__OSC32K_32K_OUT 0x4001b031 /* OSC 32Khz wifi clk in */
A Dsun8i-a83t.dtsi176 * This is called "internal OSC" in some places.
/linux-6.3-rc2/arch/alpha/kernel/
A Dsmc37c93x.c54 #define OSC 0x24 macro
/linux-6.3-rc2/Documentation/devicetree/bindings/pci/
A Drockchip,rk3399-pcie.yaml37 description: This property is needed if using 24MHz OSC for RC's PHY.
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/
A Dtesla,fsd-clock.yaml16 The root clock comes from external OSC clock (24 MHz).
/linux-6.3-rc2/Documentation/devicetree/bindings/display/samsung/
A Dsamsung,exynos-hdmi.yaml85 VDD 1.8V HDMI OSC.
/linux-6.3-rc2/drivers/clk/nxp/
A Dclk-lpc32xx.c202 LPC32XX_CLK_DEFINE(OSC, "osc", CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL),
1226 LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
/linux-6.3-rc2/drivers/pinctrl/tegra/
A Dpinctrl-tegra20.c2054 MUX_PG(cdev1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, 0x14, 4, 0x88, 2, 0xa8, 0),
2055 MUX_PG(cdev2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, 0x14, 5, 0x88, 4, 0xa8, 2),

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