/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
A D | gfx_v7_0.c | 2211 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx() 2213 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v7_0_ring_emit_ib_gfx() 2305 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in gfx_v7_0_ring_test_ib() 2473 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v7_0_cp_gfx_start() 3215 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_wreg() 4045 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch() 4053 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch() 4061 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch() 4069 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch() 4985 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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A D | gfx_v6_0.c | 1799 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush() 1813 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence() 1847 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib() 1849 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib() 1887 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib() 2003 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v6_0_cp_gfx_start() 2024 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_cp_gfx_start() 2035 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_cp_gfx_start() 2271 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_pipeline_sync() 2298 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_vm_flush() [all …]
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A D | gfx_v8_0.c | 891 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib() 1549 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds() 1575 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds() 1601 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds() 4170 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v8_0_cp_gfx_start() 4192 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v8_0_cp_gfx_start() 6094 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v8_0_ring_emit_ib_gfx() 6096 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v8_0_ring_emit_ib_gfx() 6898 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6945 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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A D | gfx_v9_0.c | 961 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg() 1045 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib() 3036 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v9_0_cp_gfx_start() 3052 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v9_0_cp_gfx_start() 4292 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in gfx_v9_0_do_edc_gds_workarounds() 5108 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v9_0_ring_emit_ib_gfx() 5110 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v9_0_ring_emit_ib_gfx() 6750 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6804 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6859 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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A D | si_enums.h | 168 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 171 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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A D | soc15d.h | 50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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A D | nvd.h | 48 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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A D | gfx_v11_0.c | 168 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx11_kiq_map_queues() 283 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v11_0_write_data_to_reg() 296 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v11_0_wait_reg_mem() 400 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v11_0_ring_test_ib() 3107 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v11_0_cp_gfx_start() 5374 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v11_0_ring_emit_ib_gfx() 5570 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v11_0_ring_emit_init_cond_exec() 5705 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v11_0_ring_emit_rreg() 6177 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 6226 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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A D | vid.h | 105 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 109 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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A D | cikd.h | 223 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 227 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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A D | gfx_v10_0.c | 3750 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v10_0_write_data_to_reg() 3859 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v10_0_ring_test_ib() 5965 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v10_0_cp_gfx_start() 5987 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v10_0_cp_gfx_start() 8409 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); in gfx_v10_0_ring_emit_ib_gfx() 8411 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v10_0_ring_emit_ib_gfx() 8623 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v10_0_ring_emit_init_cond_exec() 8798 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v10_0_ring_emit_rreg() 9258 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9314 .nop = PACKET3(PACKET3_NOP, 0x3FFF), [all …]
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A D | gfx_v9_4_2.c | 381 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_4_2_run_shader() 389 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_4_2_run_shader() 396 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 3); in gfx_v9_4_2_run_shader() 404 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); in gfx_v9_4_2_run_shader()
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A D | amdgpu_amdkfd_gfx_v11.c | 285 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v11()
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A D | amdgpu_amdkfd_gfx_v10.c | 313 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_hiq_mqd_load()
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A D | amdgpu_amdkfd_gfx_v9.c | 325 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in kgd_gfx_v9_hiq_mqd_load()
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A D | sid.h | 1658 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 1662 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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/linux-6.3-rc2/drivers/gpu/drm/radeon/ |
A D | ni.c | 1398 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit() 1404 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit() 1420 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute() 1425 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute() 1441 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute() 1547 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start() 1565 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start() 1571 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start() 1575 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start() 2691 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush() [all …]
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A D | cik.c | 3680 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma() 3730 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in cik_ring_ib_execute() 3748 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in cik_ring_ib_execute() 3789 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in cik_ib_test() 3990 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start() 5682 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush() 5696 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush() 5703 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush() 5714 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush() 8390 nop = PACKET3(PACKET3_NOP, 0x3FFF); in cik_startup() [all …]
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A D | si.c | 3379 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit() 3410 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute() 3421 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute() 3428 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute() 3576 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in si_cp_start() 3601 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start() 5075 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush() 5090 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush() 5098 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush() 5106 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush() [all …]
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A D | r600.c | 2697 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start() 2842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test() 2880 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit() 2894 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit() 2899 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit() 2937 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit() 2944 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit() 2991 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma() 3002 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); in r600_copy_cpdma() 3379 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in r600_ring_ib_execute() [all …]
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A D | r300d.h | 64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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A D | evergreen.c | 2938 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute() 2943 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute() 2949 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in evergreen_ring_ib_execute() 2956 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in evergreen_ring_ib_execute() 3010 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in evergreen_cp_start() 3029 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start() 3035 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start() 3039 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()
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A D | sid.h | 1595 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro 1599 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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A D | cikd.h | 1691 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro 1695 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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A D | rv515d.h | 204 #define PACKET3(op, n) (CP_PACKET3 | \ macro
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