Home
last modified time | relevance | path

Searched refs:PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dsi_enums.h253 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dsoc15d.h210 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dnvd.h206 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dvid.h268 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dcikd.h386 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dsid.h1839 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dgfx_v6_0.c2018 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v6_0_cp_gfx_start()
2850 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v6_0_get_csb_buffer()
A Dgfx_v7_0.c2480 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
3929 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
A Dgfx_v8_0.c1223 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4160 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
A Dgfx_v9_0.c1448 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
3026 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
A Dgfx_v11_0.c597 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v11_0_get_csb_buffer()
3097 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v11_0_cp_gfx_start()
A Dgfx_v10_0.c4103 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v10_0_get_csb_buffer()
5955 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v10_0_cp_gfx_start()
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dnid.h1262 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dsid.h1776 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dcikd.h1854 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Devergreend.h1657 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
A Dni.c1566 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cayman_cp_start()
A Dsi.c3592 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_cp_start()
5722 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_get_csb_buffer()
A Dcik.c3997 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
6711 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_get_csb_buffer()
A Devergreen.c3030 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in evergreen_cp_start()

Completed in 164 milliseconds