Home
last modified time | relevance | path

Searched refs:PACKET3_PREAMBLE_END_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dsi_enums.h254 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dsoc15d.h211 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dnvd.h207 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dvid.h269 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dcikd.h387 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dsid.h1840 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dgfx_v6_0.c2033 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v6_0_cp_gfx_start()
2874 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v6_0_get_csb_buffer()
A Dgfx_v7_0.c2504 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
3976 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
A Dgfx_v8_0.c1251 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4186 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
A Dgfx_v9_0.c1470 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
3047 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
A Dgfx_v11_0.c625 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v11_0_get_csb_buffer()
3124 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v11_0_cp_gfx_start()
A Dgfx_v10_0.c4131 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v10_0_get_csb_buffer()
5982 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v10_0_cp_gfx_start()
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dnid.h1263 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dsid.h1777 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dcikd.h1855 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Devergreend.h1658 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
A Dni.c1572 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
A Dsi.c3598 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in si_cp_start()
5764 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in si_get_csb_buffer()
A Dcik.c4007 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
6758 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_get_csb_buffer()
A Devergreen.c3036 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in evergreen_cp_start()

Completed in 157 milliseconds