| /linux-6.3-rc2/drivers/video/fbdev/nvidia/ |
| A D | nv_setup.c | 185 par->PCIO = par->PCIO0 + 0x2000; in NVSelectHeadRegisters()
190 par->PCIO = par->PCIO0; in NVSelectHeadRegisters()
411 VGA_WR08(par->PCIO, 0x03D4, 0x28); in NVCommonSetup()
458 VGA_WR08(par->PCIO, 0x03D4, 0x44); in NVCommonSetup()
461 VGA_WR08(par->PCIO, 0x03D5, 3); in NVCommonSetup()
465 VGA_WR08(par->PCIO, 0x03D4, 0x28); in NVCommonSetup()
472 VGA_WR08(par->PCIO, 0x03D4, 0x44); in NVCommonSetup()
473 VGA_WR08(par->PCIO, 0x03D5, 0); in NVCommonSetup()
477 VGA_WR08(par->PCIO, 0x03D4, 0x28); in NVCommonSetup()
611 VGA_WR08(par->PCIO, 0x03D4, 0x44); in NVCommonSetup()
[all …]
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| A D | nv_hw.c | 61 VGA_WR08(par->PCIO, 0x3D4, 0x1F); in NVLockUnlock()
64 VGA_WR08(par->PCIO, 0x3D4, 0x11); in NVLockUnlock()
65 cr11 = VGA_RD08(par->PCIO, 0x3D5); in NVLockUnlock()
70 VGA_WR08(par->PCIO, 0x3D5, cr11); in NVLockUnlock()
79 VGA_WR08(par->PCIO, 0x3D4, 0x31); in NVShowHideCursor()
1556 VGA_WR08(par->PCIO, 0x03D4, 0x19); in NVLoadStateExt()
1558 VGA_WR08(par->PCIO, 0x03D4, 0x1A); in NVLoadStateExt()
1560 VGA_WR08(par->PCIO, 0x03D4, 0x25); in NVLoadStateExt()
1562 VGA_WR08(par->PCIO, 0x03D4, 0x28); in NVLoadStateExt()
1564 VGA_WR08(par->PCIO, 0x03D4, 0x2D); in NVLoadStateExt()
[all …]
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| A D | nvidia.c | 436 VGA_WR08(par->PCIO, 0x03D4, 0x1C); in nvidia_calc_regs()
437 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); in nvidia_calc_regs()
636 VGA_WR08(par->PCIO, 0x03D4, 0x44); in nvidiafb_set_par()
637 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); in nvidiafb_set_par()
651 VGA_WR08(par->PCIO, 0x3d4, 0x46); in nvidiafb_set_par()
652 tmp = VGA_RD08(par->PCIO, 0x3d5); in nvidiafb_set_par()
654 VGA_WR08(par->PCIO, 0x3d5, tmp); in nvidiafb_set_par()
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| A D | nv_type.h | 169 volatile u8 __iomem *PCIO; member
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| /linux-6.3-rc2/drivers/video/fbdev/riva/ |
| A D | rivafb-i2c.c | 33 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
34 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; in riva_gpio_setscl()
41 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setscl()
42 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); in riva_gpio_setscl()
51 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1); in riva_gpio_setsda()
52 val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0; in riva_gpio_setsda()
60 VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1); in riva_gpio_setsda()
69 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); in riva_gpio_getscl()
70 if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04) in riva_gpio_getscl()
82 VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base); in riva_gpio_getsda()
[all …]
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| A D | riva_hw.c | 92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); in vgaLockUnlock()
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); in vgaLockUnlock()
96 VGA_WR08(chip->PCIO, 0x3D5, cr11); in vgaLockUnlock()
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); in nv4LockUnlock()
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); in ShowHideCursor()
1818 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1820 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); in SetStartAddress3()
1822 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1824 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); in SetStartAddress3()
1830 VGA_WR08(chip->PCIO, 0x3C0, 0x13); in SetStartAddress3()
[all …]
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| A D | nv_driver.c | 404 par->riva.PCIO = par->riva.PCIO0 + 0x2000; in riva_common_setup()
409 par->riva.PCIO = par->riva.PCIO0; in riva_common_setup()
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| A D | fbdev.c | 382 VGA_WR08(par->riva.PCIO, 0x3d4, index); in CRTCout()
383 VGA_WR08(par->riva.PCIO, 0x3d5, val); in CRTCout()
389 VGA_WR08(par->riva.PCIO, 0x3d4, index); in CRTCin()
390 return (VGA_RD08(par->riva.PCIO, 0x3d5)); in CRTCin()
424 VGA_WR08(par->riva.PCIO, 0x3c0, index); in ATTRout()
425 VGA_WR08(par->riva.PCIO, 0x3c0, val); in ATTRout()
431 VGA_WR08(par->riva.PCIO, 0x3c0, index); in ATTRin()
432 return (VGA_RD08(par->riva.PCIO, 0x3c1)); in ATTRin()
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| A D | riva_hw.h | 457 volatile U008 __iomem *PCIO; member
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