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Searched refs:PIPE_B (Results 1 – 25 of 37) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/i915/
A Dintel_gvt_mmio_table.c117 MMIO_D(PIPEDSL(PIPE_B)); in iterate_generic_mmio()
137 MMIO_D(CURCNTR(PIPE_B)); in iterate_generic_mmio()
140 MMIO_D(CURPOS(PIPE_B)); in iterate_generic_mmio()
143 MMIO_D(CURBASE(PIPE_B)); in iterate_generic_mmio()
164 MMIO_D(DSPCNTR(PIPE_B)); in iterate_generic_mmio()
165 MMIO_D(DSPADDR(PIPE_B)); in iterate_generic_mmio()
167 MMIO_D(DSPPOS(PIPE_B)); in iterate_generic_mmio()
168 MMIO_D(DSPSIZE(PIPE_B)); in iterate_generic_mmio()
169 MMIO_D(DSPSURF(PIPE_B)); in iterate_generic_mmio()
195 MMIO_D(SPRCTL(PIPE_B)); in iterate_generic_mmio()
[all …]
A Di915_pci.c111 [PIPE_B] = CURSOR_B_OFFSET, \
117 [PIPE_B] = CURSOR_B_OFFSET, \
124 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
131 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
177 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
242 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
333 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
387 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
418 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
535 .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
[all …]
A Di915_reg.h2282 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7716 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7730 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8027 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8030 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8033 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8036 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8052 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8055 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8058 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
A Dintel_pm.c472 case PIPE_B: in vlv_get_fifo_size()
943 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
944 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
950 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
993 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
994 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
2029 case PIPE_B: in vlv_atomic_update_fifo()
3479 if (dirty & WM_DIRTY_PIPE(PIPE_B)) in ilk_write_wm_values()
3659 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in g4x_read_wm_values()
3660 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); in g4x_read_wm_values()
[all …]
A Dintel_device_info.c403 runtime->num_scalers[PIPE_B] = 2; in intel_device_info_runtime_init()
429 runtime->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
476 runtime->pipe_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
A Di915_irq.c609 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1049 case PIPE_B: in i9xx_pipestat_irq_ack()
1482 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
1994 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
3502 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3678 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3799 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dskl_watermark.c825 [PIPE_B] = BIT(DBUF_S1),
832 [PIPE_B] = BIT(DBUF_S2),
851 [PIPE_B] = BIT(DBUF_S1),
859 [PIPE_B] = BIT(DBUF_S1),
895 [PIPE_B] = BIT(DBUF_S1),
914 [PIPE_B] = BIT(DBUF_S1),
922 [PIPE_B] = BIT(DBUF_S1),
942 [PIPE_B] = BIT(DBUF_S1),
950 [PIPE_B] = BIT(DBUF_S1),
972 [PIPE_B] = BIT(DBUF_S1),
[all …]
A Dintel_display_limits.h18 PIPE_B, enumerator
35 TRANSCODER_B = PIPE_B,
A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
395 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
475 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
579 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
756 .irq_pipe_mask = BIT(PIPE_B),
923 .irq_pipe_mask = BIT(PIPE_B),
1079 .irq_pipe_mask = BIT(PIPE_B),
1175 .irq_pipe_mask = BIT(PIPE_B),
1343 .irq_pipe_mask = BIT(PIPE_B),
1481 .irq_pipe_mask = BIT(PIPE_B),
A Dintel_dpio_phy.c697 case PIPE_B: in vlv_pipe_to_channel()
860 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
872 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
893 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
902 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
915 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
1025 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
A Dintel_display_trace.h49 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
78 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
185 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
A Dintel_pipe_crc.c177 case PIPE_B: in vlv_pipe_crc_ctl_reg()
238 case PIPE_B: in vlv_undo_pipe_scramble_reset()
A Dintel_fdi.c165 case PIPE_B: in ilk_check_fdi_lanes()
190 other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_B); in ilk_check_fdi_lanes()
292 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
316 case PIPE_B: in ivb_update_fdi_bc_bifurcation()
A Dintel_display_power_well.c1038 if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1039 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1045 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1053 intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
1353 (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1485 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
A Dg4x_hdmi.c338 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
612 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
A Dintel_pch_display.c48 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
66 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
A Dintel_pps.c38 case PIPE_B: in pps_name()
164 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
292 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1114 if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
A Di9xx_plane.c912 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
1016 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
A Dicl_dsi.c855 case PIPE_B: in gen11_dsi_configure_transcoder()
1255 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B) in icl_apply_kvmr_pipe_a_wa()
1601 if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B && in gen11_dsi_sync_state()
1744 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
A Dintel_sprite.c463 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_sprite_update_arm()
1751 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
1801 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
A Dvlv_dsi.c1061 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1086 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1915 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
/linux-6.3-rc2/drivers/gpu/drm/i915/gvt/
A Dhandlers.c2273 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2282 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2464 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2466 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2468 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2628 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2629 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2630 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2631 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2639 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
[all …]
A Dreg.h73 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
82 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
A Ddisplay.c53 pipe = PIPE_B; in get_edp_pipe()
628 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
/linux-6.3-rc2/drivers/video/fbdev/intelfb/
A Dintelfbhw.h183 #define PIPE_B 1 macro

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