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/linux-6.3-rc2/drivers/clk/mediatek/
A Dclk-mt8195-apmixedsys.c60 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
62 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
64 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
66 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
78 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
92 PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
94 PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
96 PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
98 PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
102 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
[all …]
A Dclk-mt8186-apmixedsys.c18 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ macro
54 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
60 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
62 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
64 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0,
66 PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0,
68 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0,
70 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0,
72 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
74 PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0,
[all …]
A Dclk-mt8173-apmixedsys.c42 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
59 PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, PLL_AO,
61 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, PLL_AO,
63 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
65 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7,
69 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
70 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
71 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
72 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
74 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
[all …]
A Dclk-mt6795-apmixedsys.c24 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
45 PLL(CLK_APMIXED_ARMCA53PLL, "armca53pll", 0x200, 0x20c, 0, PLL_AO,
47 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
49 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000101, HAVE_RST_BAR,
51 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0),
52 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
53 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
54 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
55 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
57 PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a8, 0x2a4, 0),
[all …]
A Dclk-mt7981-apmixed.c40 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
47 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
49 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
51 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
53 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
55 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
57 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,
59 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,
61 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
A Dclk-mt7986-apmixed.c38 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro
45 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
47 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
49 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
51 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32,
53 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0,
55 PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x0, 0, 32,
57 PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x0, 0, 32, 0x0260,
59 PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x0, 0, 32,
A Dclk-mt8195-apusys_pll.c28 #define PLL(_id, _name, _reg, _pwr_reg, _pd_reg, _pcw_reg) { \ macro
53 PLL(CLK_APUSYS_PLL_APUPLL, "apusys_pll_apupll", 0x008, 0x014, 0x00c, 0x00c),
54 PLL(CLK_APUSYS_PLL_NPUPLL, "apusys_pll_npupll", 0x018, 0x024, 0x01c, 0x01c),
55 PLL(CLK_APUSYS_PLL_APUPLL1, "apusys_pll_apupll1", 0x028, 0x034, 0x02c, 0x02c),
56 PLL(CLK_APUSYS_PLL_APUPLL2, "apusys_pll_apupll2", 0x038, 0x044, 0x03c, 0x03c),
A Dclk-mt8135.c617 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… macro
635 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
636 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
637 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2…
638 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23…
639 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
640 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
641 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
642 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
643 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
[all …]
A Dclk-mt2701.c960 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
962 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
964 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
966 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
968 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
970 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
972 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
974 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
976 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
978 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
[all …]
A Dclk-mt6797.c633 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
641 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,
643 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,
645 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,
647 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,
649 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,
651 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,
653 PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,
655 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,
657 PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,
[all …]
A Dclk-mt6779.c1186 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
1190 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
1192 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
1195 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
1198 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
1200 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
1202 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
1204 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
1207 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
1210 PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
[all …]
A Dclk-mt2712.c1226 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
1228 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
1232 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
1234 PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
1236 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
1238 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
1240 PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
1242 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
1244 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
1246 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
[all …]
A Dclk-mt7622.c46 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
332 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
334 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
336 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
338 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
340 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
342 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
344 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
346 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
348 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/
A Dqcom,mmcc.yaml83 - description: PLL 3 clock
84 - description: PLL 3 Vote clock
89 - description: HDMI phy PLL clock
121 - description: HDMI phy PLL clock
160 - description: HDMI phy PLL clock
204 - description: Global PLL 0 clock
211 - description: HDMI phy PLL clock
235 - description: Global PLL 0 clock
241 - description: HDMI phy PLL clock
264 - description: Global PLL 0 clock
[all …]
A Dqcom,a53pll.yaml7 title: Qualcomm A53 PLL clock
13 The A53 PLL on few Qualcomm platforms is the main CPU PLL used used for
48 #Example 1 - A53 PLL found on MSM8916 devices
55 #Example 2 - A53 PLL found on IPQ6018 devices
A Dxgene.txt9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
21 - clock-output-names : shall be the name of the PLL referenced by derive
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
32 Optional properties for PLL clocks:
A Dti,cdce925.yaml15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
54 "^PLL[1-4]$":
97 /* PLL options to get SSC 1% centered */
A Dbaikal,bt1-ccu-pll.yaml8 title: Baikal-T1 Clock Control Unit PLL
52 with an interface wrapper (so called safe PLL' clocks switcher) to simplify
53 the PLL configuration procedure. The PLLs work as depicted on the next
71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
73 the binding supports the PLL dividers configuration in accordance with a
81 The CCU PLL dts-node uses the common clock bindings with no custom
83 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
113 # Clock Control Unit PLL node:
A Ddove-divider-clock.txt1 PLL divider based Dove clocks
3 Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
18 - reg : shall be the register address of the Core PLL and Clock Divider
20 Core PLL and Clock Divider Control 1 register. Thus, it will have
A Dfsl,plldig.yaml14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
31 description: Optional for VCO frequency of the PLL in Hertz. The VCO frequency
32 of this PLL cannot be changed during runtime only at startup. Therefore,
35 its own desired VCO frequency for the PLL.
A Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
A Daxs10x-i2s-pll-clock.txt1 Binding for the AXS10X I2S PLL clock
9 - reg : address and length of the I2S PLL register set.
10 - clocks: shall be the input parent clock phandle for the PLL.
/linux-6.3-rc2/Documentation/devicetree/bindings/clock/ti/davinci/
A Dpll.txt1 Binding for TI DaVinci PLL Controllers
3 The PLL provides clocks to most of the components on the SoC. In addition
4 to the PLL itself, this controller also contains bypasses, gates, dividers,
26 Describes the main PLL clock output (before POSTDIV). The node name must
41 Describes the AUXCLK output of the PLL. The node name must be "auxclk".
48 Describes the OBSCLK output of the PLL. The node name must be "obsclk".
/linux-6.3-rc2/Documentation/devicetree/bindings/sound/
A Dtas2552.txt19 internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
22 defined values to select and configure the PLL and PDM reference clocks.
/linux-6.3-rc2/drivers/clk/samsung/
A Dclk-exynos5410.c240 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
242 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
244 [epll] = PLL(pll_2650x, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
246 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
248 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
250 [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,

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