| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | rk3036-cru.h | 11 #define PLL_APLL 1 macro
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| A D | rk3188-cru-common.h | 11 #define PLL_APLL 1 macro
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| A D | rk3128-cru.h | 11 #define PLL_APLL 1 macro
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| A D | rk3228-cru.h | 11 #define PLL_APLL 1 macro
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| A D | rv1108-cru.h | 11 #define PLL_APLL 0 macro
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| A D | px30-cru.h | 7 #define PLL_APLL 1 macro
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| A D | rk3288-cru.h | 11 #define PLL_APLL 1 macro
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| A D | rk3308-cru.h | 11 #define PLL_APLL 1 macro
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| A D | rk3328-cru.h | 11 #define PLL_APLL 1 macro
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| A D | rockchip,rv1126-cru.h | 65 #define PLL_APLL 1 macro
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| A D | rk3568-cru.h | 70 #define PLL_APLL 1 macro
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| /linux-6.3-rc2/drivers/clk/rockchip/ |
| A D | clk-rk3188.c | 216 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
227 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| A D | clk-rk3036.c | 137 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| A D | clk-rk3128.c | 159 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| A D | clk-rk3228.c | 169 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
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| A D | clk-rk3328.c | 215 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
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| A D | clk-rv1108.c | 154 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
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| A D | clk-rk3288.c | 226 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
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| A D | clk-px30.c | 185 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
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| A D | clk-rk3308.c | 180 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
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| A D | clk-rv1126.c | 196 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
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| A D | clk-rk3568.c | 321 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
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| /linux-6.3-rc2/arch/arm64/boot/dts/rockchip/ |
| A D | rk3328.dtsi | 807 <&cru HDMIPHY>, <&cru PLL_APLL>,
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