1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /*
3  * Microsemi Ocelot Switch driver
4  *
5  * License: Dual MIT/GPL
6  * Copyright (c) 2017 Microsemi Corporation
7  * Copyright 2020 NXP
8  */
9 
10 #ifndef _MSCC_OCELOT_PTP_H_
11 #define _MSCC_OCELOT_PTP_H_
12 
13 #include <linux/ptp_clock_kernel.h>
14 #include <soc/mscc/ocelot.h>
15 
16 #define OCELOT_MAX_PTP_ID		63
17 #define OCELOT_PTP_FIFO_SIZE		128
18 
19 #define PTP_PIN_CFG_RSZ			0x20
20 #define PTP_PIN_TOD_SEC_MSB_RSZ		PTP_PIN_CFG_RSZ
21 #define PTP_PIN_TOD_SEC_LSB_RSZ		PTP_PIN_CFG_RSZ
22 #define PTP_PIN_TOD_NSEC_RSZ		PTP_PIN_CFG_RSZ
23 #define PTP_PIN_WF_HIGH_PERIOD_RSZ	PTP_PIN_CFG_RSZ
24 #define PTP_PIN_WF_LOW_PERIOD_RSZ	PTP_PIN_CFG_RSZ
25 
26 #define PTP_PIN_CFG_DOM			BIT(0)
27 #define PTP_PIN_CFG_SYNC		BIT(2)
28 #define PTP_PIN_CFG_ACTION(x)		((x) << 3)
29 #define PTP_PIN_CFG_ACTION_MASK		PTP_PIN_CFG_ACTION(0x7)
30 
31 enum {
32 	PTP_PIN_ACTION_IDLE = 0,
33 	PTP_PIN_ACTION_LOAD,
34 	PTP_PIN_ACTION_SAVE,
35 	PTP_PIN_ACTION_CLOCK,
36 	PTP_PIN_ACTION_DELTA,
37 	PTP_PIN_ACTION_NOSYNC,
38 	PTP_PIN_ACTION_SYNC,
39 };
40 
41 #define PTP_CFG_MISC_PTP_EN		BIT(2)
42 
43 #define PTP_CFG_CLK_ADJ_CFG_ENA		BIT(0)
44 #define PTP_CFG_CLK_ADJ_CFG_DIR		BIT(1)
45 
46 #define PTP_CFG_CLK_ADJ_FREQ_NS		BIT(30)
47 
48 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
49 int ocelot_ptp_settime64(struct ptp_clock_info *ptp,
50 			 const struct timespec64 *ts);
51 int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta);
52 int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm);
53 int ocelot_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
54 		      enum ptp_pin_function func, unsigned int chan);
55 int ocelot_ptp_enable(struct ptp_clock_info *ptp,
56 		      struct ptp_clock_request *rq, int on);
57 int ocelot_init_timestamp(struct ocelot *ocelot,
58 			  const struct ptp_clock_info *info);
59 int ocelot_deinit_timestamp(struct ocelot *ocelot);
60 #endif
61