| /linux-6.3-rc2/arch/arm64/boot/dts/freescale/ |
| A D | imx8mq-nitrogen.dts | 369 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
370 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
371 MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
372 MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
373 MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
374 MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
375 MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
410 /* J13 Pin 2, WL_WAKE */
412 /* J13 Pin 4, WL_IRQ, not needed for Silex */
416 /* J13 Pin 41, BT_CLK_REQ */
[all …]
|
| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | meson8b-odroidc1.dts | 234 "J2 Header Pin 35", "J2 Header Pin 36",
235 "J2 Header Pin 32", "J2 Header Pin 31",
236 "J2 Header Pin 29", "J2 Header Pin 18",
237 "J2 Header Pin 22", "J2 Header Pin 16",
238 "J2 Header Pin 23", "J2 Header Pin 21",
239 "J2 Header Pin 19", "J2 Header Pin 33",
240 "J2 Header Pin 8", "J2 Header Pin 10",
241 "J2 Header Pin 15", "J2 Header Pin 13",
242 "J2 Header Pin 24", "J2 Header Pin 26",
245 "J2 Header Pin 7", "", "J2 Header Pin 12",
[all …]
|
| A D | imx6ull-colibri-aster.dts | 52 /* Pin already used by atmel_mxt_ts touchscreen */
58 /* Pin already used by atmel_mxt_ts touchscreen */
|
| A D | imx6ull-colibri-wifi-aster.dts | 52 /* Pin already used by atmel_mxt_ts touchscreen */
58 /* Pin already used by atmel_mxt_ts touchscreen */
|
| /linux-6.3-rc2/arch/arm64/boot/dts/hisilicon/ |
| A D | hi6220-hikey.dts | 384 "GPIO-A", /* LSEC Pin 23: GPIO2_0 */
385 "GPIO-B", /* LSEC Pin 24: GPIO2_1 */
386 "GPIO-C", /* LSEC Pin 25: GPIO2_2 */
387 "GPIO-D", /* LSEC Pin 26: GPIO2_3 */
388 "GPIO-E", /* LSEC Pin 27: GPIO2_4 */
390 "GPIO-H"; /* LSEC Pin 30: GPIO2_7 */
414 "[SPI0_DIN]", /* Pin 10: SPI0_DI */
415 "[SPI0_DOUT]", /* Pin 14: SPI0_DO */
416 "[SPI0_CS]", /* Pin 12: SPI0_CS_N */
417 "[SPI0_SCLK]", /* Pin 8: SPI0_SCLK */
[all …]
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/iio/frequency/ |
| A D | adi,adf4377.yaml | 44 GPIO that controls the Chip Enable Pin.
49 GPIO that controls the Enable Clock 1 Output Buffer Pin.
54 GPIO that controls the Enable Clock 2 Output Buffer Pin.
60 high_z - MUXOUT Pin set to high-Z.
61 lock_detect - MUXOUT Pin set to lock detector output.
62 muxout_low - MUXOUT Pin set to low.
63 f_div_rclk_2 - MUXOUT Pin set to fDIV_RCLK/2.
64 f_div_nclk_2 - MUXOUT Pin set to fDIV_NCLK/2.
65 muxout_high - MUXOUT Pin set to high.
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/pinctrl/ |
| A D | marvell,dove-pinctrl.txt | 64 pmu-nc Pin not driven by any PM function
65 pmu-low Pin driven low (0)
66 pmu-high Pin driven high (1)
67 pmic(sdi) Pin is used for PMIC SDI
68 cpu-pwr-down Pin is used for CPU_PWRDWN
69 standby-pwr-down Pin is used for STBY_PWRDWN
72 bat-fault Pin is used for BATTERY_FAULT
73 ext0-wakeup Pin is used for EXT0_WU
74 ext1-wakeup Pin is used for EXT0_WU
75 ext2-wakeup Pin is used for EXT0_WU
[all …]
|
| A D | renesas,rza1-ports.yaml | 7 title: Renesas RZ/A1 combined Pin and GPIO controller
14 The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis
150 * Pin #0 on port #3 is configured as alternate function #6.
151 * Pin #2 on port #3 is configured as alternate function #4.
160 * Pin #4 on port #1 is configured as alternate function #1.
161 * Pin #5 on port #1 is configured as alternate function #1.
176 * Pin #0 on port #4 is configured as alternate function #2
186 * Pin #1 on port #4 is configured as alternate function #1
|
| A D | cnxt,cx92755-pinctrl.txt | 1 Conexant Digicolor CX92755 General Purpose Pin Mapping
7 === Pin Controller Node ===
12 - reg: Base address of the General Purpose Pin Mapping register block and the
34 === Pin Configuration Node ===
44 === Pin Group Node ===
56 Required Pin Group Node Properties:
|
| A D | samsung,pinctrl.yaml | 80 Pin banks of the controller are represented by child nodes of the
155 /* Pin bank with external GPIO or muxed external wake-up interrupts */
185 /* Pin bank with external GPIO or muxed external wake-up interrupts */
235 /* Pin bank with external GPIO or muxed external wake-up interrupts */
243 /* Pin bank without external interrupts */
249 /* Pin bank with external direct wake-up interrupts */
320 /* Pin bank with external direct wake-up interrupts */
368 /* Pin bank with external GPIO or muxed external wake-up interrupts */
|
| A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
|
| A D | renesas,pfc.yaml | 7 title: Renesas Pin Function Controller (GPIO and Pin Mux/Config)
13 The Pin Function Controller (PFC) is a Pin Mux/Config controller.
105 Pin controller client devices use pin configuration subnodes (children
|
| A D | renesas,rzv2m-pinctrl.yaml | 7 title: Renesas RZ/V2M combined Pin and GPIO controller
14 The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
15 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
61 Pin controller client devices use pin configuration subnodes (children
|
| A D | renesas,rzg2l-pinctrl.yaml | 7 title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
14 The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
81 Pin controller client devices use pin configuration subnodes (children
|
| A D | renesas,rza2-pinctrl.yaml | 7 title: Renesas RZ/A2 combined Pin and GPIO controller
14 The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
|
| A D | ti,da850-pupd.txt | 1 * Pin configuration for TI DA850/OMAP-L138/AM18x
15 Pin Group Node Properties:
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/net/ |
| A D | mdio-mux-gpio.yaml | 61 interrupts = <10 8>; /* Pin 10, active low */
70 interrupts = <10 8>; /* Pin 10, active low */
79 interrupts = <10 8>; /* Pin 10, active low */
88 interrupts = <10 8>; /* Pin 10, active low */
104 interrupts = <12 8>; /* Pin 12, active low */
113 interrupts = <12 8>; /* Pin 12, active low */
122 interrupts = <12 8>; /* Pin 12, active low */
131 interrupts = <12 8>; /* Pin 12, active low */
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/sound/ |
| A D | rt274.txt | 18 * DMIC1 Pin
19 * DMIC2 Pin
23 * HPO Pin
|
| A D | cs4265.txt | 20 codec_ad0_high: cs4265@4f { /* AD0 Pin is high */
26 codec_ad0_low: cs4265@4e { /* AD0 Pin is low */
|
| A D | ak4613.yaml | 37 description: Input Pin 1 - 2.
41 description: Output Pin 1 - 6.
|
| /linux-6.3-rc2/rust/kernel/sync/ |
| A D | arc.rs | 28 pin::Pin,
271 impl<T: ?Sized> From<Pin<UniqueArc<T>>> for Arc<T> {
272 fn from(item: Pin<UniqueArc<T>>) -> Self { in from()
274 unsafe { Pin::into_inner_unchecked(item).inner } in from()
501 impl<T: ?Sized> From<UniqueArc<T>> for Pin<UniqueArc<T>> { implementation
505 unsafe { Pin::new_unchecked(obj) } in from()
|
| /linux-6.3-rc2/Documentation/input/devices/ |
| A D | amijoy.rst | 13 Pin Meaning Pin Meaning
27 Pin Meaning
44 Pin Meaning
61 Pin Meaning
78 Pin Meaning
152 | Directions | Pin# | Counter bits |
|
| /linux-6.3-rc2/rust/alloc/ |
| A D | boxed.rs | 153 use core::pin::Pin;
265 pub fn pin(x: T) -> Pin<Box<T>> { in pin()
553 pub const fn pin_in(x: T, alloc: A) -> Pin<Self> in pin_in()
1170 pub const fn into_pin(boxed: Self) -> Pin<Self> in into_pin()
1177 unsafe { Pin::new_unchecked(boxed) } in into_pin()
1407 impl<T: ?Sized, A: Allocator> const From<Box<T, A>> for Pin<Box<T, A>> implementation
1988 G::resume(Pin::new(&mut *self), arg) in resume()
1993 impl<G: ?Sized + Generator<R>, R, A: Allocator> Generator<R> for Pin<Box<G, A>> implementation
2012 fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> { in poll()
2013 F::poll(Pin::new(&mut *self), cx) in poll()
[all …]
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/gpio/ |
| A D | xlnx,zynqmp-gpio-modepin.yaml | 7 title: ZynqMP Mode Pin GPIO controller
10 PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin
|
| /linux-6.3-rc2/Documentation/devicetree/bindings/arm/hisilicon/ |
| A D | low-pin-count.yaml | 7 title: Hisilicon HiP06 Low Pin Count device
13 Hisilicon HiP06 SoCs implement a Low Pin Count (LPC) controller, which
|