1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  *  Bluetooth supports for Qualcomm Atheros ROME chips
4  *
5  *  Copyright (c) 2015 The Linux Foundation. All rights reserved.
6  */
7 
8 #define EDL_PATCH_CMD_OPCODE		(0xFC00)
9 #define EDL_NVM_ACCESS_OPCODE		(0xFC0B)
10 #define EDL_WRITE_BD_ADDR_OPCODE	(0xFC14)
11 #define EDL_PATCH_CMD_LEN		(1)
12 #define EDL_PATCH_VER_REQ_CMD		(0x19)
13 #define EDL_PATCH_TLV_REQ_CMD		(0x1E)
14 #define EDL_GET_BUILD_INFO_CMD		(0x20)
15 #define EDL_NVM_ACCESS_SET_REQ_CMD	(0x01)
16 #define EDL_PATCH_CONFIG_CMD		(0x28)
17 #define MAX_SIZE_PER_TLV_SEGMENT	(243)
18 #define QCA_PRE_SHUTDOWN_CMD		(0xFC08)
19 #define QCA_DISABLE_LOGGING		(0xFC17)
20 
21 #define EDL_CMD_REQ_RES_EVT		(0x00)
22 #define EDL_PATCH_VER_RES_EVT		(0x19)
23 #define EDL_APP_VER_RES_EVT		(0x02)
24 #define EDL_TVL_DNLD_RES_EVT		(0x04)
25 #define EDL_CMD_EXE_STATUS_EVT		(0x00)
26 #define EDL_SET_BAUDRATE_RSP_EVT	(0x92)
27 #define EDL_NVM_ACCESS_CODE_EVT		(0x0B)
28 #define EDL_PATCH_CONFIG_RES_EVT	(0x00)
29 #define QCA_DISABLE_LOGGING_SUB_OP	(0x14)
30 
31 #define EDL_TAG_ID_HCI			(17)
32 #define EDL_TAG_ID_DEEP_SLEEP		(27)
33 
34 #define QCA_WCN3990_POWERON_PULSE	0xFC
35 #define QCA_WCN3990_POWEROFF_PULSE	0xC0
36 
37 #define QCA_HCI_CC_OPCODE		0xFC00
38 #define QCA_HCI_CC_SUCCESS		0x00
39 
40 #define QCA_WCN3991_SOC_ID		(0x40014320)
41 
42 /* QCA chipset version can be decided by patch and SoC
43  * version, combination with upper 2 bytes from SoC
44  * and lower 2 bytes from patch will be used.
45  */
46 #define get_soc_ver(soc_id, rom_ver)	\
47 	((le32_to_cpu(soc_id) << 16) | (le16_to_cpu(rom_ver)))
48 
49 #define QCA_FW_BUILD_VER_LEN		255
50 
51 
52 enum qca_baudrate {
53 	QCA_BAUDRATE_115200 	= 0,
54 	QCA_BAUDRATE_57600,
55 	QCA_BAUDRATE_38400,
56 	QCA_BAUDRATE_19200,
57 	QCA_BAUDRATE_9600,
58 	QCA_BAUDRATE_230400,
59 	QCA_BAUDRATE_250000,
60 	QCA_BAUDRATE_460800,
61 	QCA_BAUDRATE_500000,
62 	QCA_BAUDRATE_720000,
63 	QCA_BAUDRATE_921600,
64 	QCA_BAUDRATE_1000000,
65 	QCA_BAUDRATE_1250000,
66 	QCA_BAUDRATE_2000000,
67 	QCA_BAUDRATE_3000000,
68 	QCA_BAUDRATE_4000000,
69 	QCA_BAUDRATE_1600000,
70 	QCA_BAUDRATE_3200000,
71 	QCA_BAUDRATE_3500000,
72 	QCA_BAUDRATE_AUTO 	= 0xFE,
73 	QCA_BAUDRATE_RESERVED
74 };
75 
76 enum qca_tlv_dnld_mode {
77 	QCA_SKIP_EVT_NONE,
78 	QCA_SKIP_EVT_VSE,
79 	QCA_SKIP_EVT_CC,
80 	QCA_SKIP_EVT_VSE_CC
81 };
82 
83 enum qca_tlv_type {
84 	TLV_TYPE_PATCH = 1,
85 	TLV_TYPE_NVM,
86 	ELF_TYPE_PATCH,
87 };
88 
89 struct qca_fw_config {
90 	u8 type;
91 	char fwname[64];
92 	uint8_t user_baud_rate;
93 	enum qca_tlv_dnld_mode dnld_mode;
94 	enum qca_tlv_dnld_mode dnld_type;
95 };
96 
97 struct edl_event_hdr {
98 	__u8 cresp;
99 	__u8 rtype;
100 	__u8 data[];
101 } __packed;
102 
103 struct qca_btsoc_version {
104 	__le32 product_id;
105 	__le16 patch_ver;
106 	__le16 rom_ver;
107 	__le32 soc_id;
108 } __packed;
109 
110 struct tlv_seg_resp {
111 	__u8 result;
112 } __packed;
113 
114 struct tlv_type_patch {
115 	__le32 total_size;
116 	__le32 data_length;
117 	__u8   format_version;
118 	__u8   signature;
119 	__u8   download_mode;
120 	__u8   reserved1;
121 	__le16 product_id;
122 	__le16 rom_build;
123 	__le16 patch_version;
124 	__le16 reserved2;
125 	__le32 entry;
126 } __packed;
127 
128 struct tlv_type_nvm {
129 	__le16 tag_id;
130 	__le16 tag_len;
131 	__le32 reserve1;
132 	__le32 reserve2;
133 	__u8   data[];
134 } __packed;
135 
136 struct tlv_type_hdr {
137 	__le32 type_len;
138 	__u8   data[];
139 } __packed;
140 
141 enum qca_btsoc_type {
142 	QCA_INVALID = -1,
143 	QCA_AR3002,
144 	QCA_ROME,
145 	QCA_WCN3990,
146 	QCA_WCN3998,
147 	QCA_WCN3991,
148 	QCA_QCA6390,
149 	QCA_WCN6750,
150 };
151 
152 #if IS_ENABLED(CONFIG_BT_QCA)
153 
154 int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr);
155 int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
156 		   enum qca_btsoc_type soc_type, struct qca_btsoc_version ver,
157 		   const char *firmware_name);
158 int qca_read_soc_version(struct hci_dev *hdev, struct qca_btsoc_version *ver,
159 			 enum qca_btsoc_type);
160 int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr);
161 int qca_send_pre_shutdown_cmd(struct hci_dev *hdev);
qca_is_wcn399x(enum qca_btsoc_type soc_type)162 static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
163 {
164 	return soc_type == QCA_WCN3990 || soc_type == QCA_WCN3991 ||
165 	       soc_type == QCA_WCN3998;
166 }
qca_is_wcn6750(enum qca_btsoc_type soc_type)167 static inline bool qca_is_wcn6750(enum qca_btsoc_type soc_type)
168 {
169 	return soc_type == QCA_WCN6750;
170 }
171 
172 #else
173 
qca_set_bdaddr_rome(struct hci_dev * hdev,const bdaddr_t * bdaddr)174 static inline int qca_set_bdaddr_rome(struct hci_dev *hdev, const bdaddr_t *bdaddr)
175 {
176 	return -EOPNOTSUPP;
177 }
178 
qca_uart_setup(struct hci_dev * hdev,uint8_t baudrate,enum qca_btsoc_type soc_type,struct qca_btsoc_version ver,const char * firmware_name)179 static inline int qca_uart_setup(struct hci_dev *hdev, uint8_t baudrate,
180 				 enum qca_btsoc_type soc_type,
181 				 struct qca_btsoc_version ver,
182 				 const char *firmware_name)
183 {
184 	return -EOPNOTSUPP;
185 }
186 
qca_read_soc_version(struct hci_dev * hdev,struct qca_btsoc_version * ver,enum qca_btsoc_type)187 static inline int qca_read_soc_version(struct hci_dev *hdev,
188 				       struct qca_btsoc_version *ver,
189 				       enum qca_btsoc_type)
190 {
191 	return -EOPNOTSUPP;
192 }
193 
qca_set_bdaddr(struct hci_dev * hdev,const bdaddr_t * bdaddr)194 static inline int qca_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr)
195 {
196 	return -EOPNOTSUPP;
197 }
198 
qca_is_wcn399x(enum qca_btsoc_type soc_type)199 static inline bool qca_is_wcn399x(enum qca_btsoc_type soc_type)
200 {
201 	return false;
202 }
203 
qca_is_wcn6750(enum qca_btsoc_type soc_type)204 static inline bool qca_is_wcn6750(enum qca_btsoc_type soc_type)
205 {
206 	return false;
207 }
208 
qca_send_pre_shutdown_cmd(struct hci_dev * hdev)209 static inline int qca_send_pre_shutdown_cmd(struct hci_dev *hdev)
210 {
211 	return -EOPNOTSUPP;
212 }
213 #endif
214