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Searched refs:RCS0 (Results 1 – 21 of 21) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/gvt/
A Dmmio_context.c52 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
53 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
84 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
123 {RCS0, TRVADR, 0, true}, /* 0x4df0 */
124 {RCS0, TRTTE, 0, true}, /* 0x4df4 */
125 {RCS0, _MMIO(0x4dfc), 0, true},
159 [RCS0] = 0xc800,
322 if (req->engine->id != RCS0) in intel_vgpu_restore_inhibit_context()
346 [RCS0] = 0x4260,
403 [RCS0] = 0xc800, in switch_mocs()
[all …]
A Dscheduler.c101 if (workload->engine->id != RCS0) in sr_oa_regs()
165 if (workload->engine->id == RCS0) { in populate_shadow_context()
218 if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0) in populate_shadow_context()
505 if (workload->engine->id == RCS0 && in intel_gvt_scan_and_shadow_workload()
977 if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0) in update_guest_context()
1703 if (engine->id == RCS0) { in intel_vgpu_create_workload()
A Dexeclist.c49 [RCS0] = RCS_AS_CONTEXT_SWITCH,
A Dcmd_parser.c425 #define R_RCS BIT(RCS0)
597 [RCS0] = {
1051 if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) { in cmd_handler_lri()
1152 [RCS0] = {
A Dhandlers.c321 engine_mask |= BIT(RCS0); in gdrst_mmio_write()
2076 id = RCS0; in gvt_reg_tlb_control_handler()
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_pci.c187 .__runtime.platform_engine_mask = BIT(RCS0), \
208 .__runtime.platform_engine_mask = BIT(RCS0), \
246 .__runtime.platform_engine_mask = BIT(RCS0), \
338 .__runtime.platform_engine_mask = BIT(RCS0), \
371 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
381 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0),
390 .__runtime.platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
914 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
933 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
1052 BIT(RCS0) | BIT(BCS0) |
[all …]
A Di915_drv.h751 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
A Di915_irq.c3613 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); in i8xx_irq_handler()
3721 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir); in i915_irq_handler()
3866 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], in i965_irq_handler()
A Di915_gpu_error.c1286 case RCS0: in engine_record_registers()
/linux-6.3-rc2/drivers/gpu/drm/i915/selftests/
A Dmock_gem_device.c215 to_gt(i915)->engine[RCS0] = mock_engine(i915, "mock", RCS0); in mock_gem_device()
216 if (!to_gt(i915)->engine[RCS0]) in mock_gem_device()
219 if (mock_engine_init(to_gt(i915)->engine[RCS0])) in mock_gem_device()
A Di915_request.c218 ce = i915_gem_context_get_engine(ctx[0], RCS0); in igt_request_rewind()
236 ce = i915_gem_context_get_engine(ctx[1], RCS0); in igt_request_rewind()
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dselftest_engine_cs.c148 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in perf_mi_bb_start()
275 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in perf_mi_noop()
A Dselftest_gt_pm.c103 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in live_gt_clocks()
A Dintel_engine_cs.c63 [RCS0] = {
402 [RCS0] = GEN11_GRDOM_RENDER, in get_reset_domain()
435 [RCS0] = GEN6_GRDOM_RENDER, in get_reset_domain()
1566 [RCS0] = MSG_IDLE_CS, in __cs_pending_mi_force_wakes()
1649 if (engine->id != RCS0) in intel_engine_get_instdone()
1683 if (engine->id != RCS0) in intel_engine_get_instdone()
1695 if (engine->id == RCS0) in intel_engine_get_instdone()
A Dintel_engine_types.h109 RCS0 = 0, enumerator
A Dintel_engine_user.c164 [RENDER_CLASS] = { RCS0, 1 }, in legacy_ring_idx()
A Dintel_ring_submission.c93 case RCS0: in set_hwsp()
940 GEM_BUG_ON(engine->id != RCS0); in switch_context()
A Dintel_mocs.c569 [RCS0] = __GEN9_RCS0_MOCS0, in mocs_offset()
A Dintel_execlists_submission.c3496 [RCS0] = GEN8_RCS_IRQ_SHIFT, in logical_ring_default_irqs()
/linux-6.3-rc2/drivers/gpu/drm/i915/gem/
A Di915_gem_execbuffer.c2224 if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) { in i915_reset_gen7_sol_offsets()
2476 [I915_EXEC_DEFAULT] = RCS0,
2477 [I915_EXEC_RENDER] = RCS0,
/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_overlay.c1392 engine = to_gt(dev_priv)->engine[RCS0]; in intel_overlay_setup()

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