Searched refs:REGV_RD32 (Results 1 – 3 of 3) sorted by relevance
88 u32 gen_ctrl = REGV_RD32(MTL_VPU_HOST_SS_GEN_CTRL); in ivpu_hw_read_platform()258 u32 val = REGV_RD32(MTL_VPU_HOST_SS_CPR_RST_CLR); in ivpu_boot_host_ss_rst_clr_assert()269 u32 val = REGV_RD32(MTL_VPU_HOST_SS_CPR_RST_SET); in ivpu_boot_host_ss_rst_drive()303 u32 val = REGV_RD32(MTL_VPU_HOST_SS_NOC_QREQN); in ivpu_boot_noc_qreqn_check()323 u32 val = REGV_RD32(MTL_VPU_HOST_SS_NOC_QDENY); in ivpu_boot_noc_qdeny_check()333 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN); in ivpu_boot_top_noc_qrenqn_check()344 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QACCEPTN); in ivpu_boot_top_noc_qacceptn_check()355 u32 val = REGV_RD32(MTL_VPU_TOP_NOC_QDENY); in ivpu_boot_top_noc_qdeny_check()381 val = REGV_RD32(MTL_VPU_HOST_SS_NOC_QREQN); in ivpu_boot_host_ss_axi_drive()416 val = REGV_RD32(MTL_VPU_TOP_NOC_QREQN); in ivpu_boot_host_ss_top_noc_drive()[all …]
243 val = REGV_RD32(MTL_VPU_HOST_MMU_IDR0); in ivpu_mmu_config_check()247 val = REGV_RD32(MTL_VPU_HOST_MMU_IDR1); in ivpu_mmu_config_check()251 val = REGV_RD32(MTL_VPU_HOST_MMU_IDR3); in ivpu_mmu_config_check()262 val = REGV_RD32(MTL_VPU_HOST_MMU_IDR5); in ivpu_mmu_config_check()804 evtq->prod = REGV_RD32(MTL_VPU_HOST_MMU_EVTQ_PROD_SEC); in ivpu_mmu_get_event()844 gerror_val = REGV_RD32(MTL_VPU_HOST_MMU_GERROR); in ivpu_mmu_irq_gerr_handler()845 gerrorn_val = REGV_RD32(MTL_VPU_HOST_MMU_GERRORN); in ivpu_mmu_irq_gerr_handler()
24 #define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__) macro
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