Home
last modified time | relevance | path

Searched refs:REG_BIT (Results 1 – 21 of 21) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_hdcp_regs.h13 #define HDCP_AKSV_SEND_TRIGGER REG_BIT(31)
14 #define HDCP_CLEAR_KEYS_TRIGGER REG_BIT(30)
15 #define HDCP_KEY_LOAD_TRIGGER REG_BIT(8)
17 #define HDCP_FUSE_IN_PROGRESS REG_BIT(7)
18 #define HDCP_FUSE_ERROR REG_BIT(6)
19 #define HDCP_FUSE_DONE REG_BIT(5)
20 #define HDCP_KEY_LOAD_STATUS REG_BIT(1)
21 #define HDCP_KEY_LOAD_DONE REG_BIT(0)
47 #define HDCP_SHA1_BUSY REG_BIT(16)
48 #define HDCP_SHA1_READY REG_BIT(17)
[all …]
A Dintel_dvo_regs.h15 #define DVO_ENABLE REG_BIT(31)
16 #define DVO_PIPE_SEL_MASK REG_BIT(30)
22 #define DVO_INTERRUPT_SELECT REG_BIT(27)
25 #define DVO_USE_VGA_SYNC REG_BIT(15)
26 #define DVO_DATA_ORDER_MASK REG_BIT(14)
29 #define DVO_VSYNC_DISABLE REG_BIT(11)
30 #define DVO_HSYNC_DISABLE REG_BIT(10)
31 #define DVO_VSYNC_TRISTATE REG_BIT(9)
32 #define DVO_HSYNC_TRISTATE REG_BIT(8)
33 #define DVO_BORDER_ENABLE REG_BIT(7)
[all …]
A Dintel_snps_phy_regs.h29 #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
30 #define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
31 #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
35 #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
36 #define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
37 #define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
39 #define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
42 #define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
43 #define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
51 #define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
[all …]
A Dintel_audio_regs.h12 #define G4X_ELD_VALID REG_BIT(14)
15 #define G4X_ELD_ACK REG_BIT(4)
28 #define IBX_ELD_ACK REG_BIT(4)
58 #define AUD_CONFIG_N_VALUE_INDEX REG_BIT(29)
59 #define AUD_CONFIG_N_PROG_ENABLE REG_BIT(28)
81 #define AUD_CONFIG_DISABLE_NCTS REG_BIT(3)
94 #define AUD_M_CTS_M_VALUE_INDEX REG_BIT(21)
95 #define AUD_M_CTS_M_PROG_ENABLE REG_BIT(20)
122 #define AUD_ENABLE_SDP_SPLIT REG_BIT(31)
129 #define AUD_PIN_BUF_ENABLE REG_BIT(31)
[all …]
A Dintel_dmc_regs.h19 #define PIPEDMC_ENABLE REG_BIT(0)
22 #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
53 #define DMC_EVT_CTL_ENABLE REG_BIT(31)
54 #define DMC_EVT_CTL_RECURRING REG_BIT(30)
A Dintel_hti_regs.h13 #define HDPORT_DDI_USED(phy) REG_BIT(2 * (phy) + 1)
14 #define HDPORT_ENABLED REG_BIT(0)
A Dintel_combo_phy_regs.h154 #define ICL_PORT_TX_DW8_ODCC_CLK_SEL REG_BIT(31)
160 #define ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP REG_BIT(7)
A Dintel_dkl_phy_regs.h54 #define DKL_PCS_DW5_CORE_SOFTRESET REG_BIT(11)
149 #define DKL_TX_DP20BITMODE REG_BIT(2)
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_gt_regs.h353 #define AUX_INV REG_BIT(0)
416 #define TBIMR_FAST_CLIP REG_BIT(5)
528 #define EN_32B_ACCESS REG_BIT(30)
753 #define CG3DDISURB REG_BIT(14)
928 #define IDLE_MSG_DISABLE REG_BIT(0)
981 #define XEHPC_OVRLSCCC REG_BIT(0)
1037 #define TDONRENDER REG_BIT(2)
1048 #define FLUSHALLNONCOH REG_BIT(5)
1157 #define DISABLE_ECC REG_BIT(5)
1467 #define BCS_SRC_Y REG_BIT(0)
[all …]
A Dintel_engine_regs.h51 #define GEN6_BSD_GO_INDICATOR REG_BIT(4)
52 #define GEN6_BSD_SLEEP_INDICATOR REG_BIT(3)
75 #define MI_FLUSH_ENABLE REG_BIT(12)
76 #define TGL_NESTED_BB_EN REG_BIT(12)
77 #define MODE_IDLE REG_BIT(9)
78 #define STOP_RING REG_BIT(8)
79 #define VS_TIMER_DISPATCH REG_BIT(6)
104 #define RESET_CTL_CAT_ERROR REG_BIT(2)
125 #define ECO_GATING_CX_ONLY REG_BIT(3)
127 #define ECO_FLIP_DONE REG_BIT(0)
[all …]
A Dintel_gpu_commands.h136 #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
156 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)
157 #define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
178 #define MI_LRR_SOURCE_CS_MMIO REG_BIT(18)
188 #define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
256 #define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
257 #define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
372 #define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
373 #define MFX_WAIT_DW0_PXP_SYNC_CONTROL_FLAG REG_BIT(9)
400 #define BASE_ADDRESS_MODIFY REG_BIT(0)
[all …]
A Dintel_gtt.h77 #define GEN6_PTE_VALID REG_BIT(0)
83 #define GEN6_PDE_VALID REG_BIT(0)
88 #define BYT_PTE_SNOOPED_BY_CPU_CACHES REG_BIT(2)
89 #define BYT_PTE_WRITEABLE REG_BIT(1)
132 #define CHV_PPAT_SNOOP REG_BIT(6)
A Dintel_migrate.c406 *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); /* as qword elements */ in emit_pte()
439 *cs++ = MI_STORE_DATA_IMM | REG_BIT(21); in emit_pte()
A Dselftest_lrc.c958 poison &= ~REG_BIT(0); in safe_poison()
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_reg.h120 #define LMEM_INIT REG_BIT(7)
121 #define DRIVERFLR REG_BIT(31)
1078 #define MBUS_JOIN REG_BIT(31)
1267 #define FBC_CTL_EN REG_BIT(31)
1758 #define RATL_MASK REG_BIT(5)
2704 #define PP_ON REG_BIT(31)
2712 #define PP_READY REG_BIT(30)
4304 #define DVS_TILED REG_BIT(10)
4501 #define SP_TILED REG_BIT(10)
7744 #define SGGI_DIS REG_BIT(15)
[all …]
A Dintel_mchbar_regs.h190 #define DG1_QCLK_REFERENCE REG_BIT(10)
220 #define PKG_PWR_LIM_1_EN REG_BIT(15)
241 #define DG1_GEAR_TYPE REG_BIT(16)
A Di915_perf_oa_regs.h138 #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30)
139 #define GEN12_SQCNT1_OABPC REG_BIT(29)
A Di915_reg_defs.h20 #define REG_BIT(__n) \ macro
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/uc/abi/
A Dguc_actions_slpc_abi.h156 #define SLPC_GTPERF_TASK_ENABLED REG_BIT(0)
157 #define SLPC_DCC_TASK_ENABLED REG_BIT(11)
158 #define SLPC_IN_DCC REG_BIT(12)
159 #define SLPC_BALANCER_ENABLED REG_BIT(15)
160 #define SLPC_IBC_TASK_ENABLED REG_BIT(16)
161 #define SLPC_BALANCER_IA_LMT_ENABLED REG_BIT(17)
162 #define SLPC_BALANCER_IA_LMT_ACTIVE REG_BIT(18)
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/uc/
A Dintel_gsc_fw.c15 #define GSC_FW_INIT_COMPLETE_BIT REG_BIT(9)
/linux-6.3-rc2/drivers/gpu/drm/i915/pxp/
A Dintel_pxp.c66 #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)

Completed in 86 milliseconds