Searched refs:REG_DSI_14nm_PHY_CMN_CLK_CFG0 (Results 1 – 2 of 2) sorted by relevance
611 val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; in dsi_pll_14nm_postdiv_recalc_rate()653 val = dsi_phy_read(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); in dsi_pll_14nm_postdiv_set_rate()657 dsi_phy_write(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); in dsi_pll_14nm_postdiv_set_rate()666 dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, val); in dsi_pll_14nm_postdiv_set_rate()691 data = dsi_phy_read(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); in dsi_14nm_pll_save_state()723 dsi_phy_write(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); in dsi_14nm_pll_restore_state()730 dsi_phy_write(slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0, data); in dsi_14nm_pll_restore_state()
64 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010 macro
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