Searched refs:REG_DSI_28nm_PHY_PLL_CAL_CFG1 (Results 1 – 2 of 2) sorted by relevance
330 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070 macro
400 dsi_phy_write_ndelay(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34, 500); in dsi_pll_28nm_vco_prepare_lp()
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