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Searched refs:REG_FIELD_PREP (Results 1 – 22 of 22) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/i915/display/
A Dintel_snps_phy.c102 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
128 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
149 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
170 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
196 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
230 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
275 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
306 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
369 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
416 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
[all …]
A Dintel_dvo_regs.h17 #define DVO_PIPE_SEL(pipe) REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe))
19 #define DVO_PIPE_STALL_UNUSED REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0)
20 #define DVO_PIPE_STALL REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1)
21 #define DVO_PIPE_STALL_TV REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2)
27 #define DVO_DATA_ORDER_I740 REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0)
28 #define DVO_DATA_ORDER_FP REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1)
35 #define DVO_ACT_DATA_ORDER_RGGB REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
36 #define DVO_ACT_DATA_ORDER_GBRG REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
37 #define DVO_ACT_DATA_ORDER_GBRG_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0)
38 #define DVO_ACT_DATA_ORDER_RGGB_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1)
[all …]
A Dintel_audio_regs.h64 #define AUD_CONFIG_N(n) (REG_FIELD_PREP(AUD_CONFIG_UPPER_N_MASK, (n) >> 12) | \
65 REG_FIELD_PREP(AUD_CONFIG_LOWER_N_MASK, (n) & 0xfff))
67 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 0)
68 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 1)
69 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 2)
70 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 3)
71 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 4)
72 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 5)
73 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 6)
74 #define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 REG_FIELD_PREP(AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK, 7)
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A Dintel_dkl_phy_regs.h60 #define DKL_PLL_DIV0_AFC_STARTUP(val) REG_FIELD_PREP(DKL_PLL_DIV0_AFC_STARTUP_MASK, (val))
151 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_…
153 #define DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(val) REG_FIELD_PREP(DKL_TX_DPCNTL2_CFG_LOADGENSELECT_…
A Dintel_color.c479 REG_FIELD_PREP(PALETTE_GREEN_MASK, _i9xx_lut_10_ldw(color[0].green)) | in i9xx_lut_10_ldw()
480 REG_FIELD_PREP(PALETTE_BLUE_MASK, _i9xx_lut_10_ldw(color[0].blue)); in i9xx_lut_10_ldw()
546 return REG_FIELD_PREP(PALETTE_RED_MASK, color->red & 0xff) | in i965_lut_10p6_ldw()
547 REG_FIELD_PREP(PALETTE_GREEN_MASK, color->green & 0xff) | in i965_lut_10p6_ldw()
548 REG_FIELD_PREP(PALETTE_BLUE_MASK, color->blue & 0xff); in i965_lut_10p6_ldw()
554 return REG_FIELD_PREP(PALETTE_RED_MASK, color->red >> 8) | in i965_lut_10p6_udw()
555 REG_FIELD_PREP(PALETTE_GREEN_MASK, color->green >> 8) | in i965_lut_10p6_udw()
556 REG_FIELD_PREP(PALETTE_BLUE_MASK, color->blue >> 8); in i965_lut_10p6_udw()
594 REG_FIELD_PREP(PREC_PALETTE_12P4_BLUE_LDW_MASK, color->blue & 0x3f); in ilk_lut_12p4_ldw()
601 REG_FIELD_PREP(PREC_PALETTE_12P4_GREEN_UDW_MASK, color->green >> 6) | in ilk_lut_12p4_udw()
[all …]
A Dintel_lvds.c219 …REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps-… in intel_lvds_pps_init_hw()
222 …REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, … in intel_lvds_pps_init_hw()
225 …REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_M… in intel_lvds_pps_init_hw()
A Dicl_dsi_regs.h34 #define TX_ESC_CLK_DIV_PHY REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
102 #define TGL_DSI_CHKN_LSHS_GB(byte_clocks) REG_FIELD_PREP(TGL_DSI_CHKN_LSHS_GB_MASK, \
A Dintel_pps.c1503 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in pps_init_registers()
1504 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); in pps_init_registers()
1505 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | in pps_init_registers()
1506 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in pps_init_registers()
1539 …REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_… in pps_init_registers()
1545 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); in pps_init_registers()
A Dintel_dmc.c285 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, in disable_event_handler()
287 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, in disable_event_handler()
303 REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK, in disable_flip_queue_event()
305 REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK, in disable_flip_queue_event()
A Dintel_combo_phy_regs.h156 #define ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_DIV2 REG_FIELD_PREP(ICL_PORT_TX_DW8_ODCC_CLK_DIV_SEL_MAS…
A Dskl_watermark.c2241 val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); in skl_write_wm_level()
2242 val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); in skl_write_wm_level()
/linux-6.3-rc2/drivers/gpu/drm/i915/
A Di915_reg.h616 #define PORT_PLL_N(n) REG_FIELD_PREP(PORT_PLL_N_MASK, (n))
1301 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
4209 #define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
4482 #define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2)
4507 #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
4509 #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
4514 #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
6219 #define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
6220 #define TRANS_BPC_10 REG_FIELD_PREP(TRANS_BPC_MASK, 1)
6221 #define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
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A Dintel_pcode.c224 mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd) in snb_pcode_read_p()
225 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1) in snb_pcode_read_p()
226 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2); in snb_pcode_read_p()
240 mbox = REG_FIELD_PREP(GEN6_PCODE_MB_COMMAND, mbcmd) in snb_pcode_write_p()
241 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM1, p1) in snb_pcode_write_p()
242 | REG_FIELD_PREP(GEN6_PCODE_MB_PARAM2, p2); in snb_pcode_write_p()
A Di915_reg_defs.h70 #define REG_FIELD_PREP(__mask, __val) \ macro
A Di915_hwmon.c113 REG_FIELD_PREP(PKG_PWR_LIM_1, nval)); in hwm_field_scale_and_write()
241 rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y); in hwm_power1_max_interval_store()
/linux-6.3-rc2/drivers/gpu/drm/i915/gt/
A Dintel_gpu_commands.h248 REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
250 REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
262 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
264 REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
A Dintel_engine_regs.h136 (REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (dst) << 1) | \
137 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (src) << 1))
153 (REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, (write) << 1) | \
154 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, (read) << 1))
A Dintel_gt_irq.c315 REG_FIELD_PREP(ENGINE0_MASK, guc_mask) : in gen11_gt_irq_postinstall()
316 REG_FIELD_PREP(ENGINE1_MASK, guc_mask); in gen11_gt_irq_postinstall()
319 REG_FIELD_PREP(ENGINE1_MASK, guc_mask)); in gen11_gt_irq_postinstall()
A Dintel_gt_regs.h426 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
428 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
967 #define GEN11_HASH_CTRL_EXCL_BIT0 REG_FIELD_PREP(GEN11_HASH_CTRL_EXCL_MASK, 0x1)
1045 #define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
1171 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
1198 #define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)
A Dintel_gt_mcr.c264 REG_FIELD_PREP(MTL_MCR_GROUPID, group) | in rw_with_mcr_steering_fw()
265 REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance) | in rw_with_mcr_steering_fw()
A Dintel_workarounds.c672 REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)); in dg2_ctx_gt_tuning_init()
3050 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); in general_render_compute_wa_init()
A Dintel_lrc.c1345 *cs++ = REG_FIELD_PREP(VERT_WM_VAL, 0x3FF); in dg2_emit_draw_watermark_setting()

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