Searched refs:REG_FIELD_SHIFT (Results 1 – 6 of 6) sorted by relevance
| /linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/ |
| A D | soc15_common.h | 45 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
53 ~REG_FIELD_MASK(reg_name, field)) | (val) << REG_FIELD_SHIFT(reg_name, field), \
193 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
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| A D | amdgpu.h | 1206 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT macro
1211 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1214 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1217 …WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, fi…
1220 …t, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
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| A D | uvd_v5_0.c | 688 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | in uvd_v5_0_set_sw_clock_gating()
689 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); in uvd_v5_0_set_sw_clock_gating()
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| A D | uvd_v6_0.c | 1345 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | in uvd_v6_0_set_sw_clock_gating()
1346 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); in uvd_v6_0_set_sw_clock_gating()
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| A D | uvd_v7_0.c | 1627 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1628 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
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| /linux-6.3-rc2/drivers/accel/habanalabs/common/ |
| A D | habanalabs.h | 2542 #define REG_FIELD_SHIFT(reg, field) reg##_##field##_SHIFT macro
2547 (val) << REG_FIELD_SHIFT(reg, field))
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