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Searched refs:REG_OFDM0_TRX_PATH_ENABLE (Results 1 – 6 of 6) sorted by relevance

/linux-6.3-rc2/drivers/net/wireless/realtek/rtl8xxxu/
A Drtl8xxxu_8188f.c1088 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, in rtl8188fu_phy_iqcalibrate()
1122 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8188fu_phy_iqcalibrate()
1617 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188f_enable_rf()
1620 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188f_enable_rf()
1629 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188f_disable_rf()
1631 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188f_disable_rf()
A Drtl8xxxu_8188e.c792 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, in rtl8188eu_phy_iqcalibrate()
832 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8188eu_phy_iqcalibrate()
1288 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188e_enable_rf()
1291 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188e_enable_rf()
1300 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188e_disable_rf()
1302 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188e_disable_rf()
A Drtl8xxxu_8723b.c935 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, in rtl8723bu_phy_iqcalibrate()
966 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8723bu_phy_iqcalibrate()
A Drtl8xxxu_8192e.c1142 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, in rtl8192eu_phy_iqcalibrate()
1173 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8192eu_phy_iqcalibrate()
A Drtl8xxxu_core.c1010 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8xxxu_gen1_enable_rf()
1018 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8xxxu_gen1_enable_rf()
1051 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8xxxu_gen1_disable_rf()
1053 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8xxxu_gen1_disable_rf()
2216 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8xxxu_init_phy_bb()
2220 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8xxxu_init_phy_bb()
3063 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, in rtl8xxxu_phy_iqcalibrate()
3101 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8xxxu_phy_iqcalibrate()
A Drtl8xxxu_regs.h1013 #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04 macro

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