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Searched refs:RREG32 (Results 1 – 25 of 177) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dradeon_bios.c269 bus_cntl = RREG32(R600_BUS_CNTL); in ni_read_disabled_bios()
273 rom_cntl = RREG32(R600_ROM_CNTL); in ni_read_disabled_bios()
316 bus_cntl = RREG32(R600_BUS_CNTL); in r700_read_disabled_bios()
320 rom_cntl = RREG32(R600_ROM_CNTL); in r700_read_disabled_bios()
389 bus_cntl = RREG32(R600_BUS_CNTL); in r600_read_disabled_bios()
393 rom_cntl = RREG32(R600_ROM_CNTL); in r600_read_disabled_bios()
464 bus_cntl = RREG32(RV370_BUS_CNTL); in avivo_read_disabled_bios()
468 gpiopad_a = RREG32(RADEON_GPIOPAD_A); in avivo_read_disabled_bios()
469 gpiopad_en = RREG32(RADEON_GPIOPAD_EN); in avivo_read_disabled_bios()
524 bus_cntl = RREG32(RV370_BUS_CNTL); in legacy_read_disabled_bios()
[all …]
A Dradeon_legacy_encoders.c656 dac_cntl = RREG32(RADEON_DAC_CNTL); in radeon_legacy_primary_dac_detect()
1220 dac_cntl = RREG32(RADEON_DAC_CNTL); in radeon_legacy_tv_dac_mode_set()
1309 gpiopad_a = RREG32(RADEON_GPIOPAD_A); in r300_legacy_tv_detect()
1310 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); in r300_legacy_tv_detect()
1338 RREG32(RADEON_TV_DAC_CNTL); in r300_legacy_tv_detect()
1349 RREG32(RADEON_TV_DAC_CNTL); in r300_legacy_tv_detect()
1352 tmp = RREG32(RADEON_TV_DAC_CNTL); in r300_legacy_tv_detect()
1382 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); in radeon_legacy_tv_detect()
1418 tmp = RREG32(RADEON_TV_DAC_CNTL); in radeon_legacy_tv_detect()
1463 tmp = RREG32(RADEON_GPIO_MONID); in radeon_legacy_ext_dac_detect()
[all …]
A Dvce_v2_0.c44 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
48 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
52 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
58 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
63 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_sw_cg()
68 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING); in vce_v2_0_set_sw_cg()
78 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
88 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_set_dyn_cg()
135 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
141 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
[all …]
A Dradeon_i2c.c182 val = RREG32(rec->y_clk_reg); in get_clock()
197 val = RREG32(rec->y_data_reg); in get_data()
474 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
477 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
506 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
509 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
534 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
537 tmp = RREG32(i2c_cntl_0); in r100_hw_i2c_xfer()
604 tmp = RREG32(rec->a_clk_reg); in r500_hw_i2c_xfer()
607 tmp = RREG32(rec->a_clk_reg); in r500_hw_i2c_xfer()
[all …]
A Dvce_v1_0.c64 return RREG32(VCE_RB_RPTR); in vce_v1_0_get_rptr()
66 return RREG32(VCE_RB_RPTR2); in vce_v1_0_get_rptr()
81 return RREG32(VCE_RB_WPTR); in vce_v1_0_get_wptr()
83 return RREG32(VCE_RB_WPTR2); in vce_v1_0_get_wptr()
108 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
112 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_enable_mgcg()
121 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_enable_mgcg()
140 tmp = RREG32(VCE_CLOCK_GATING_A); in vce_v1_0_init_cg()
144 tmp = RREG32(VCE_CLOCK_GATING_B); in vce_v1_0_init_cg()
149 tmp = RREG32(VCE_UENC_CLOCK_GATING); in vce_v1_0_init_cg()
[all …]
A Drs600.c239 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
248 tmp = RREG32(voltage->gpio.reg); in rs600_pm_misc()
479 tmp = RREG32(RADEON_CP_RB_CNTL); in rs600_asic_reset()
491 RREG32(R_0000F0_RBBM_SOFT_RESET); in rs600_asic_reset()
499 RREG32(R_0000F0_RBBM_SOFT_RESET); in rs600_asic_reset()
507 RREG32(R_0000F0_RBBM_SOFT_RESET); in rs600_asic_reset()
715 RREG32(R_000040_GEN_INT_CNTL); in rs600_irq_set()
1054 RREG32(R_000E40_RBBM_STATUS), in rs600_resume()
1055 RREG32(R_0007C0_CP_STAT)); in rs600_resume()
1129 RREG32(R_000E40_RBBM_STATUS), in rs600_init()
[all …]
A Drv730_dpm.c200 RREG32(CG_SPLL_FUNC_CNTL); in rv730_read_clock_registers()
202 RREG32(CG_SPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
204 RREG32(CG_SPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
206 RREG32(CG_SPLL_SPREAD_SPECTRUM); in rv730_read_clock_registers()
208 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); in rv730_read_clock_registers()
211 RREG32(TCI_MCLK_PWRMGT_CNTL); in rv730_read_clock_registers()
213 RREG32(TCI_DLL_CNTL); in rv730_read_clock_registers()
215 RREG32(CG_MPLL_FUNC_CNTL); in rv730_read_clock_registers()
217 RREG32(CG_MPLL_FUNC_CNTL_2); in rv730_read_clock_registers()
219 RREG32(CG_MPLL_FUNC_CNTL_3); in rv730_read_clock_registers()
[all …]
A Dr600.c127 r = RREG32(R600_RCU_DATA); in r600_rcu_rreg()
183 *val = RREG32(reg); in r600_get_allowed_info_register()
1442 tmp = RREG32(RAMCFG); in r600_mc_init()
1450 tmp = RREG32(CHMAP); in r600_mc_init()
1581 RREG32(CP_STAT)); in r600_print_gpu_status_regs()
1857 tmp = RREG32(BUS_CNTL); in r600_gpu_pci_config_reset()
2380 tmp = RREG32(ARB_POP); in r600_gpu_init()
2847 tmp = RREG32(scratch); in r600_ring_test()
3436 tmp = RREG32(scratch); in r600_ib_test()
4107 RREG32(IH_RB_WPTR); in r600_irq_process()
[all …]
A Drs400.c247 tmp = RREG32(RADEON_MC_STATUS); in rs400_mc_wait_for_idle()
262 RREG32(RADEON_MC_STATUS)); in rs400_gpu_init()
290 r = RREG32(RS480_NB_MC_DATA); in rs400_mc_rreg()
313 tmp = RREG32(RADEON_HOST_PATH_CNTL); in rs400_debugfs_gart_info_show()
315 tmp = RREG32(RADEON_BUS_CNTL); in rs400_debugfs_gart_info_show()
331 tmp = RREG32(RADEON_AGP_BASE); in rs400_debugfs_gart_info_show()
333 tmp = RREG32(RS480_AGP_BASE_2); in rs400_debugfs_gart_info_show()
472 RREG32(R_000E40_RBBM_STATUS), in rs400_resume()
473 RREG32(R_0007C0_CP_STAT)); in rs400_resume()
546 RREG32(R_000E40_RBBM_STATUS), in rs400_init()
[all …]
A Dr100.c751 RREG32(RADEON_GEN_INT_CNTL); in r100_irq_set()
2558 tmp = RREG32(RADEON_BUS_CNTL); in r100_bm_disable()
2794 tom = RREG32(RADEON_NB_TOM); in r100_vram_init_sizes()
3032 tmp = RREG32(RADEON_BUS_CNTL); in r100_debugfs_mc_info_show()
3036 tmp = RREG32(RADEON_AGP_BASE); in r100_debugfs_mc_info_show()
3040 tmp = RREG32(0x01D0); in r100_debugfs_mc_info_show()
3046 tmp = RREG32(0x01E4); in r100_debugfs_mc_info_show()
3671 tmp = RREG32(scratch); in r100_ring_test()
3748 tmp = RREG32(scratch); in r100_ib_test()
3946 RREG32(R_0007C0_CP_STAT)); in r100_resume()
[all …]
A Dcik.c169 *val = RREG32(reg); in cik_get_allowed_info_register()
244 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
245 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
256 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
258 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
3470 tmp = RREG32(scratch); in cik_ring_test()
3815 tmp = RREG32(scratch); in cik_ib_test()
4796 RREG32(GRBM_STATUS)); in cik_print_gpu_status_regs()
4798 RREG32(GRBM_STATUS2)); in cik_print_gpu_status_regs()
4808 RREG32(SRBM_STATUS)); in cik_print_gpu_status_regs()
[all …]
/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dgmc_v8_0.c382 data = RREG32(mmMC_SEQ_MISC0); in gmc_v8_0_polaris_mc_load_microcode()
775 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v8_0_set_prt()
850 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_enable()
859 tmp = RREG32(mmVM_L2_CNTL2); in gmc_v8_0_gart_enable()
865 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v8_0_gart_enable()
871 tmp = RREG32(mmVM_L2_CNTL4); in gmc_v8_0_gart_enable()
985 tmp = RREG32(mmVM_L2_CNTL); in gmc_v8_0_gart_disable()
1534 data = RREG32(mmVM_L2_CG); in fiji_update_mc_medium_grain_clock_gating()
1570 data = RREG32(mmVM_L2_CG); in fiji_update_mc_medium_grain_clock_gating()
1614 data = RREG32(mmVM_L2_CG); in fiji_update_mc_light_sleep()
[all …]
A Dgmc_v7_0.c274 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
299 tmp = RREG32(mmHDP_MISC_CNTL); in gmc_v7_0_mc_program()
326 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v7_0_mc_init()
332 tmp = RREG32(mmMC_SHARED_CHMAP); in gmc_v7_0_mc_init()
521 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v7_0_set_fault_enable_default()
552 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v7_0_set_prt()
627 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_enable()
641 tmp = RREG32(mmVM_L2_CNTL3); in gmc_v7_0_gart_enable()
695 tmp = RREG32(mmCHUB_CONTROL); in gmc_v7_0_gart_enable()
745 tmp = RREG32(mmVM_L2_CNTL); in gmc_v7_0_gart_disable()
[all …]
A Damdgpu_i2c.c51 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
57 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; in amdgpu_i2c_pre_xfer()
60 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; in amdgpu_i2c_pre_xfer()
64 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; in amdgpu_i2c_pre_xfer()
73 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_pre_xfer()
77 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_pre_xfer()
92 temp = RREG32(rec->mask_clk_reg); in amdgpu_i2c_post_xfer()
96 temp = RREG32(rec->mask_data_reg); in amdgpu_i2c_post_xfer()
109 val = RREG32(rec->y_clk_reg); in amdgpu_i2c_get_clock()
124 val = RREG32(rec->y_data_reg); in amdgpu_i2c_get_data()
[all …]
A Dvce_v2_0.c60 return RREG32(mmVCE_RB_RPTR); in vce_v2_0_ring_get_rptr()
62 return RREG32(mmVCE_RB_RPTR2); in vce_v2_0_ring_get_rptr()
77 return RREG32(mmVCE_RB_WPTR); in vce_v2_0_ring_get_wptr()
79 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
151 tmp = RREG32(mmVCE_CLOCK_GATING_A); in vce_v2_0_init_cg()
157 tmp = RREG32(mmVCE_UENC_CLOCK_GATING); in vce_v2_0_init_cg()
162 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_init_cg()
294 status = RREG32(mmVCE_LMI_STATUS); in vce_v2_0_stop()
315 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
329 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
[all …]
A Dgmc_v6_0.c239 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v6_0_mc_program()
271 tmp = RREG32(mmMC_ARB_RAMCFG); in gmc_v6_0_mc_init()
279 tmp = RREG32(mmMC_SHARED_CHMAP); in gmc_v6_0_mc_init()
391 tmp = RREG32(mmVM_CONTEXT1_CNTL); in gmc_v6_0_set_fault_enable_default()
422 tmp = RREG32(mmVM_PRT_CNTL); in gmc_v6_0_set_prt()
816 u32 tmp = RREG32(mmMC_SEQ_MISC0); in gmc_v6_0_sw_init()
956 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v6_0_is_idle()
983 u32 tmp = RREG32(mmSRBM_STATUS); in gmc_v6_0_soft_reset()
1003 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v6_0_soft_reset()
1007 tmp = RREG32(mmSRBM_SOFT_RESET); in gmc_v6_0_soft_reset()
[all …]
A Dcz_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_enable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_disable_interrupts()
148 ih_cntl = RREG32(mmIH_CNTL); in cz_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
215 tmp = RREG32(mmIH_RB_CNTL); in cz_ih_get_wptr()
348 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_is_idle()
364 tmp = RREG32(mmSRBM_STATUS); in cz_ih_wait_for_idle()
376 u32 tmp = RREG32(mmSRBM_STATUS); in cz_ih_soft_reset()
383 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset()
387 tmp = RREG32(mmSRBM_SOFT_RESET); in cz_ih_soft_reset()
[all …]
A Diceland_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_enable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_disable_interrupts()
148 ih_cntl = RREG32(mmIH_CNTL); in iceland_ih_irq_init()
201 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
214 tmp = RREG32(mmIH_RB_CNTL); in iceland_ih_get_wptr()
342 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_is_idle()
358 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_wait_for_idle()
370 u32 tmp = RREG32(mmSRBM_STATUS); in iceland_ih_soft_reset()
377 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset()
381 tmp = RREG32(mmSRBM_SOFT_RESET); in iceland_ih_soft_reset()
[all …]
A Dcik_ih.c62 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_enable_interrupts()
63 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_enable_interrupts()
81 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in cik_ih_disable_interrupts()
82 u32 ih_cntl = RREG32(mmIH_CNTL); in cik_ih_disable_interrupts()
117 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in cik_ih_irq_init()
204 tmp = RREG32(mmIH_RB_CNTL); in cik_ih_get_wptr()
351 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_is_idle()
380 u32 tmp = RREG32(mmSRBM_STATUS); in cik_ih_soft_reset()
386 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
390 tmp = RREG32(mmSRBM_SOFT_RESET); in cik_ih_soft_reset()
[all …]
A Dsi_ih.c37 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_enable_interrupts()
38 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts()
49 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts()
50 u32 ih_cntl = RREG32(IH_CNTL); in si_ih_disable_interrupts()
71 interrupt_cntl = RREG32(INTERRUPT_CNTL); in si_ih_irq_init()
119 tmp = RREG32(IH_RB_CNTL); in si_ih_get_wptr()
216 u32 tmp = RREG32(SRBM_STATUS); in si_ih_is_idle()
242 u32 tmp = RREG32(SRBM_STATUS); in si_ih_soft_reset()
248 tmp = RREG32(SRBM_SOFT_RESET); in si_ih_soft_reset()
252 tmp = RREG32(SRBM_SOFT_RESET); in si_ih_soft_reset()
[all …]
A Damdgpu_amdkfd_gfx_v7.c213 (*dump)[i++][1] = RREG32(addr); \ in kgd_hqd_dump()
328 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
333 if (low == RREG32(mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
334 high == RREG32(mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
396 temp = RREG32(mmCP_HQD_IQ_TIMER); in kgd_hqd_destroy()
425 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); in kgd_hqd_destroy()
444 temp = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
470 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); in kgd_hqd_sdma_destroy()
487 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | in kgd_hqd_sdma_destroy()
524 value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); in get_atc_vmid_pasid_mapping_info()
[all …]
A Dvce_v3_0.c90 v = RREG32(mmVCE_RB_RPTR); in vce_v3_0_ring_get_rptr()
92 v = RREG32(mmVCE_RB_RPTR2); in vce_v3_0_ring_get_rptr()
94 v = RREG32(mmVCE_RB_RPTR3); in vce_v3_0_ring_get_rptr()
122 v = RREG32(mmVCE_RB_WPTR); in vce_v3_0_ring_get_wptr()
124 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
126 v = RREG32(mmVCE_RB_WPTR3); in vce_v3_0_ring_get_wptr()
182 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
208 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
685 tmp = RREG32(mmSRBM_SOFT_RESET); in vce_v3_0_soft_reset()
689 tmp = RREG32(mmSRBM_SOFT_RESET); in vce_v3_0_soft_reset()
[all …]
A Dgfx_v7_0.c2321 tmp = RREG32(mmSCRATCH_REG0); in gfx_v7_0_ring_test_ib()
2596 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2604 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
3045 tmp = RREG32(mmCP_CPF_DEBUG); in gfx_v7_0_cp_compute_resume()
3288 tmp = RREG32(mmRLC_LB_CNTL); in gfx_v7_0_enable_lbpw()
3330 tmp = RREG32(mmRLC_CNTL); in gfx_v7_0_update_rlc()
3551 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3552 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
3553 RREG32(mmCB_CGTT_SCLK_CTRL); in gfx_v7_0_enable_cgcg()
4588 tmp = RREG32(mmGRBM_STATUS); in gfx_v7_0_soft_reset()
[all …]
A Duvd_v3_1.c48 return RREG32(mmUVD_RBC_RB_RPTR); in uvd_v3_1_ring_get_rptr()
62 return RREG32(mmUVD_RBC_RB_WPTR); in uvd_v3_1_ring_get_wptr()
155 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v3_1_ring_test_ring()
213 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
358 tmp = RREG32(mmUVD_MPC_CNTL); in uvd_v3_1_start()
385 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
456 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop()
467 status = RREG32(mmUVD_LMI_STATUS); in uvd_v3_1_stop()
481 status = RREG32(mmUVD_LMI_STATUS); in uvd_v3_1_stop()
607 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
[all …]
A Dtonga_ih.c62 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_enable_interrupts()
79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); in tonga_ih_disable_interrupts()
113 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); in tonga_ih_irq_init()
203 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
218 tmp = RREG32(mmIH_RB_CNTL); in tonga_ih_get_wptr()
359 u32 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_is_idle()
375 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_wait_for_idle()
387 u32 tmp = RREG32(mmSRBM_STATUS); in tonga_ih_check_soft_reset()
434 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset()
438 tmp = RREG32(mmSRBM_SOFT_RESET); in tonga_ih_soft_reset()
[all …]

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