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Searched refs:RREG32_PCIE (Results 1 – 25 of 36) sorted by relevance

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/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dnbio_v6_1.c169 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_update_medium_grain_clock_gating()
197 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_update_medium_grain_light_sleep()
218 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_get_clockgating_state()
223 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_get_clockgating_state()
274 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); in nbio_v6_1_init_registers()
314 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v6_1_program_aspm()
321 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v6_1_program_aspm()
331 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v6_1_program_aspm()
361 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v6_1_program_aspm()
383 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v6_1_program_aspm()
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A Dnbio_v2_3.c236 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_update_medium_grain_clock_gating()
265 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_update_medium_grain_light_sleep()
286 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_get_clockgating_state()
291 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_get_clockgating_state()
356 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_enable_aspm()
412 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_program_aspm()
419 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v2_3_program_aspm()
429 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v2_3_program_aspm()
459 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v2_3_program_aspm()
481 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_program_aspm()
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A Dnbio_v7_4.c260 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_update_medium_grain_light_sleep()
281 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_4_get_clockgating_state()
286 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_get_clockgating_state()
683 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); in nbio_v7_4_program_ltr()
708 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v7_4_program_aspm()
715 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v7_4_program_aspm()
725 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v7_4_program_aspm()
730 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); in nbio_v7_4_program_aspm()
755 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v7_4_program_aspm()
777 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v7_4_program_aspm()
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A Dumc_v6_1.c50 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_enable_umc_index_mode()
65 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_disable_umc_index_mode()
80 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_get_umc_index_mode_state()
119 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
132 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
197 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
202 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
212 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
412 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_err_cnt_init_per_channel()
A Dcik.c1589 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()
1629 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1633 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1680 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1744 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in cik_program_aspm()
1749 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in cik_program_aspm()
1860 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in cik_program_aspm()
1868 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()
1871 data = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_program_aspm()
1953 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in cik_get_pcie_usage()
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A Dvi.c1130 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_enable_aspm()
1165 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_program_aspm()
1179 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in vi_program_aspm()
1184 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in vi_program_aspm()
1251 orig = data = RREG32_PCIE(ixCPM_CONTROL); in vi_program_aspm()
1290 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in vi_program_aspm()
1291 data1 = RREG32_PCIE(ixPCIE_LC_STATUS1); in vi_program_aspm()
1422 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in vi_get_pcie_usage()
1436 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in vi_get_pcie_replay_count()
1803 temp = data = RREG32_PCIE(ixPCIE_CNTL2); in vi_update_bif_medium_grain_light_sleep()
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A Dumc_v8_7.c192 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
205 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
252 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
257 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
267 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
402 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_err_cnt_init_per_channel()
A Dnbio_v7_0.c154 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); in nbio_v7_0_update_medium_grain_clock_gating()
192 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_update_medium_grain_light_sleep()
213 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_0_get_clockgating_state()
218 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_get_clockgating_state()
A Dumc_v6_7.c287 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
292 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
302 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
381 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()
394 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()
520 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + in umc_v6_7_query_ras_poison_mode_per_channel()
A Damdgpu_xgmi.c956 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_query_ras_error_count()
963 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_query_ras_error_count()
972 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_query_ras_error_count()
979 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_query_ras_error_count()
988 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
990 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
997 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
999 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_query_ras_error_count()
A Dsoc15.c782 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); in soc15_get_pcie_usage()
787 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in soc15_get_pcie_usage()
788 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in soc15_get_pcie_usage()
831 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); in vega20_get_pcie_usage()
836 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); in vega20_get_pcie_usage()
837 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); in vega20_get_pcie_usage()
872 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); in soc15_get_pcie_replay_count()
873 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); in soc15_get_pcie_replay_count()
A Dsi.c1617 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in si_get_pcie_usage()
1622 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in si_get_pcie_usage()
1623 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in si_get_pcie_usage()
1631 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in si_get_pcie_replay_count()
1632 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); in si_get_pcie_replay_count()
2291 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
2472 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
2635 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
2643 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
A Dpsp_v3_1.c302 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); in psp_v3_1_smu_reload_quirk()
A Damdgpu_cgs.c64 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
A Dumc_v8_10.c327 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_10_err_cnt_init_per_channel()
A Dgmc_v7_0.c858 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in gmc_v7_0_enable_bif_mgls()
A Damdgpu.h1161 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) macro
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dr300.c93 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
95 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
178 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()
198 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()
595 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info_show()
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info_show()
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); in rv370_debugfs_pcie_gart_info_show()
601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); in rv370_debugfs_pcie_gart_info_show()
603 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); in rv370_debugfs_pcie_gart_info_show()
605 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); in rv370_debugfs_pcie_gart_info_show()
[all …]
A Dsi.c5567 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_enable_bif_mgls()
7146 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
7289 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
7452 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
7460 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/smumgr/
A Dsmu9_smumgr.c44 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu9_is_smc_ram_running()
A Dvega20_smumgr.c54 mp1_fw_flags = RREG32_PCIE(MP1_Public | in vega20_is_smc_ram_running()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Dsmu_v13_0.c164 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_load_microcode()
238 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
242 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
2055 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v13_0_get_current_pcie_link_width_level()
2075 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v13_0_get_current_pcie_link_speed_level()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/swsmu/smu12/
A Dsmu_v12_0.c63 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v12_0_check_fw_status()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Dsmu_v11_0.c169 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_load_microcode()
188 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_check_fw_status()
2083 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v11_0_get_current_pcie_link_width_level()
2103 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v11_0_get_current_pcie_link_speed_level()
/linux-6.3-rc2/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega12_hwmgr.c2228 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in vega12_get_current_pcie_link_width_level()
2248 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in vega12_get_current_pcie_link_speed_level()

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