Searched refs:RREG32_UVD_CTX (Results 1 – 9 of 9) sorted by relevance
368 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v3_1_start()603 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()612 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v3_1_enable_mgcg()
326 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL); in uvd_v4_2_start()610 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()619 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v4_2_enable_mgcg()
769 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()778 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v5_0_enable_mgcg()
68 return RREG32_UVD_CTX(index); in amdgpu_cgs_read_ind_register()
1429 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()1438 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); in uvd_v6_0_enable_mgcg()
1169 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) macro
5452 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()5464 tmp = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in si_enable_uvd_mgcg()
2571 #define RREG32_UVD_CTX(reg) r600_uvd_ctx_rreg(rdev, (reg)) macro
6208 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in cik_enable_uvd_mgcg()6217 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL); in cik_enable_uvd_mgcg()
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