1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Intel MAX 10 Board Management Controller chip.
4 *
5 * Copyright (C) 2018-2020 Intel Corporation, Inc.
6 */
7 #ifndef __MFD_INTEL_M10_BMC_H
8 #define __MFD_INTEL_M10_BMC_H
9
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/dev_printk.h>
13 #include <linux/regmap.h>
14
15 #define M10BMC_N3000_LEGACY_BUILD_VER 0x300468
16 #define M10BMC_N3000_SYS_BASE 0x300800
17 #define M10BMC_N3000_SYS_END 0x300fff
18 #define M10BMC_N3000_FLASH_BASE 0x10000000
19 #define M10BMC_N3000_FLASH_END 0x1fffffff
20 #define M10BMC_N3000_MEM_END M10BMC_N3000_FLASH_END
21
22 #define M10BMC_STAGING_BASE 0x18000000
23 #define M10BMC_STAGING_SIZE 0x3800000
24
25 /* Register offset of system registers */
26 #define NIOS2_N3000_FW_VERSION 0x0
27 #define M10BMC_N3000_MAC_LOW 0x10
28 #define M10BMC_N3000_MAC_BYTE4 GENMASK(7, 0)
29 #define M10BMC_N3000_MAC_BYTE3 GENMASK(15, 8)
30 #define M10BMC_N3000_MAC_BYTE2 GENMASK(23, 16)
31 #define M10BMC_N3000_MAC_BYTE1 GENMASK(31, 24)
32 #define M10BMC_N3000_MAC_HIGH 0x14
33 #define M10BMC_N3000_MAC_BYTE6 GENMASK(7, 0)
34 #define M10BMC_N3000_MAC_BYTE5 GENMASK(15, 8)
35 #define M10BMC_N3000_MAC_COUNT GENMASK(23, 16)
36 #define M10BMC_N3000_TEST_REG 0x3c
37 #define M10BMC_N3000_BUILD_VER 0x68
38 #define M10BMC_N3000_VER_MAJOR_MSK GENMASK(23, 16)
39 #define M10BMC_N3000_VER_PCB_INFO_MSK GENMASK(31, 24)
40 #define M10BMC_N3000_VER_LEGACY_INVALID 0xffffffff
41
42 /* Secure update doorbell register, in system register region */
43 #define M10BMC_N3000_DOORBELL 0x400
44
45 /* Authorization Result register, in system register region */
46 #define M10BMC_N3000_AUTH_RESULT 0x404
47
48 /* Doorbell register fields */
49 #define DRBL_RSU_REQUEST BIT(0)
50 #define DRBL_RSU_PROGRESS GENMASK(7, 4)
51 #define DRBL_HOST_STATUS GENMASK(11, 8)
52 #define DRBL_RSU_STATUS GENMASK(23, 16)
53 #define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24)
54 #define DRBL_PKVL1_POLL_EN BIT(25)
55 #define DRBL_PKVL2_POLL_EN BIT(26)
56 #define DRBL_CONFIG_SEL BIT(28)
57 #define DRBL_REBOOT_REQ BIT(29)
58 #define DRBL_REBOOT_DISABLED BIT(30)
59
60 /* Progress states */
61 #define RSU_PROG_IDLE 0x0
62 #define RSU_PROG_PREPARE 0x1
63 #define RSU_PROG_READY 0x3
64 #define RSU_PROG_AUTHENTICATING 0x4
65 #define RSU_PROG_COPYING 0x5
66 #define RSU_PROG_UPDATE_CANCEL 0x6
67 #define RSU_PROG_PROGRAM_KEY_HASH 0x7
68 #define RSU_PROG_RSU_DONE 0x8
69 #define RSU_PROG_PKVL_PROM_DONE 0x9
70
71 /* Device and error states */
72 #define RSU_STAT_NORMAL 0x0
73 #define RSU_STAT_TIMEOUT 0x1
74 #define RSU_STAT_AUTH_FAIL 0x2
75 #define RSU_STAT_COPY_FAIL 0x3
76 #define RSU_STAT_FATAL 0x4
77 #define RSU_STAT_PKVL_REJECT 0x5
78 #define RSU_STAT_NON_INC 0x6
79 #define RSU_STAT_ERASE_FAIL 0x7
80 #define RSU_STAT_WEAROUT 0x8
81 #define RSU_STAT_NIOS_OK 0x80
82 #define RSU_STAT_USER_OK 0x81
83 #define RSU_STAT_FACTORY_OK 0x82
84 #define RSU_STAT_USER_FAIL 0x83
85 #define RSU_STAT_FACTORY_FAIL 0x84
86 #define RSU_STAT_NIOS_FLASH_ERR 0x85
87 #define RSU_STAT_FPGA_FLASH_ERR 0x86
88
89 #define HOST_STATUS_IDLE 0x0
90 #define HOST_STATUS_WRITE_DONE 0x1
91 #define HOST_STATUS_ABORT_RSU 0x2
92
93 #define rsu_prog(doorbell) FIELD_GET(DRBL_RSU_PROGRESS, doorbell)
94
95 /* interval 100ms and timeout 5s */
96 #define NIOS_HANDSHAKE_INTERVAL_US (100 * 1000)
97 #define NIOS_HANDSHAKE_TIMEOUT_US (5 * 1000 * 1000)
98
99 /* RSU PREP Timeout (2 minutes) to erase flash staging area */
100 #define RSU_PREP_INTERVAL_MS 100
101 #define RSU_PREP_TIMEOUT_MS (2 * 60 * 1000)
102
103 /* RSU Complete Timeout (40 minutes) for full flash update */
104 #define RSU_COMPLETE_INTERVAL_MS 1000
105 #define RSU_COMPLETE_TIMEOUT_MS (40 * 60 * 1000)
106
107 /* Addresses for security related data in FLASH */
108 #define M10BMC_N3000_BMC_REH_ADDR 0x17ffc004
109 #define M10BMC_N3000_BMC_PROG_ADDR 0x17ffc000
110 #define M10BMC_N3000_BMC_PROG_MAGIC 0x5746
111
112 #define M10BMC_N3000_SR_REH_ADDR 0x17ffd004
113 #define M10BMC_N3000_SR_PROG_ADDR 0x17ffd000
114 #define M10BMC_N3000_SR_PROG_MAGIC 0x5253
115
116 #define M10BMC_N3000_PR_REH_ADDR 0x17ffe004
117 #define M10BMC_N3000_PR_PROG_ADDR 0x17ffe000
118 #define M10BMC_N3000_PR_PROG_MAGIC 0x5250
119
120 /* Address of 4KB inverted bit vector containing staging area FLASH count */
121 #define M10BMC_N3000_STAGING_FLASH_COUNT 0x17ffb000
122
123 #define M10BMC_N6000_INDIRECT_BASE 0x400
124
125 #define M10BMC_N6000_SYS_BASE 0x0
126 #define M10BMC_N6000_SYS_END 0xfff
127
128 #define M10BMC_N6000_DOORBELL 0x1c0
129 #define M10BMC_N6000_AUTH_RESULT 0x1c4
130 #define AUTH_RESULT_RSU_STATUS GENMASK(23, 16)
131
132 #define M10BMC_N6000_BUILD_VER 0x0
133 #define NIOS2_N6000_FW_VERSION 0x4
134 #define M10BMC_N6000_MAC_LOW 0x20
135 #define M10BMC_N6000_MAC_HIGH (M10BMC_N6000_MAC_LOW + 4)
136
137 /* Addresses for security related data in FLASH */
138 #define M10BMC_N6000_BMC_REH_ADDR 0x7ffc004
139 #define M10BMC_N6000_BMC_PROG_ADDR 0x7ffc000
140 #define M10BMC_N6000_BMC_PROG_MAGIC 0x5746
141
142 #define M10BMC_N6000_SR_REH_ADDR 0x7ffd004
143 #define M10BMC_N6000_SR_PROG_ADDR 0x7ffd000
144 #define M10BMC_N6000_SR_PROG_MAGIC 0x5253
145
146 #define M10BMC_N6000_PR_REH_ADDR 0x7ffe004
147 #define M10BMC_N6000_PR_PROG_ADDR 0x7ffe000
148 #define M10BMC_N6000_PR_PROG_MAGIC 0x5250
149
150 #define M10BMC_N6000_STAGING_FLASH_COUNT 0x7ff5000
151
152 #define M10BMC_N6000_FLASH_MUX_CTRL 0x1d0
153 #define M10BMC_N6000_FLASH_MUX_SELECTION GENMASK(2, 0)
154 #define M10BMC_N6000_FLASH_MUX_IDLE 0
155 #define M10BMC_N6000_FLASH_MUX_NIOS 1
156 #define M10BMC_N6000_FLASH_MUX_HOST 2
157 #define M10BMC_N6000_FLASH_MUX_PFL 4
158 #define get_flash_mux(mux) FIELD_GET(M10BMC_N6000_FLASH_MUX_SELECTION, mux)
159
160 #define M10BMC_N6000_FLASH_NIOS_REQUEST BIT(4)
161 #define M10BMC_N6000_FLASH_HOST_REQUEST BIT(5)
162
163 #define M10BMC_N6000_FLASH_CTRL 0x40
164 #define M10BMC_N6000_FLASH_WR_MODE BIT(0)
165 #define M10BMC_N6000_FLASH_RD_MODE BIT(1)
166 #define M10BMC_N6000_FLASH_BUSY BIT(2)
167 #define M10BMC_N6000_FLASH_FIFO_SPACE GENMASK(13, 4)
168 #define M10BMC_N6000_FLASH_READ_COUNT GENMASK(25, 16)
169
170 #define M10BMC_N6000_FLASH_ADDR 0x44
171 #define M10BMC_N6000_FLASH_FIFO 0x800
172 #define M10BMC_N6000_READ_BLOCK_SIZE 0x800
173 #define M10BMC_N6000_FIFO_MAX_BYTES 0x800
174 #define M10BMC_N6000_FIFO_WORD_SIZE 4
175 #define M10BMC_N6000_FIFO_MAX_WORDS (M10BMC_N6000_FIFO_MAX_BYTES / \
176 M10BMC_N6000_FIFO_WORD_SIZE)
177
178 #define M10BMC_FLASH_INT_US 1
179 #define M10BMC_FLASH_TIMEOUT_US 10000
180
181 /**
182 * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map
183 */
184 struct m10bmc_csr_map {
185 unsigned int base;
186 unsigned int build_version;
187 unsigned int fw_version;
188 unsigned int mac_low;
189 unsigned int mac_high;
190 unsigned int doorbell;
191 unsigned int auth_result;
192 unsigned int bmc_prog_addr;
193 unsigned int bmc_reh_addr;
194 unsigned int bmc_magic;
195 unsigned int sr_prog_addr;
196 unsigned int sr_reh_addr;
197 unsigned int sr_magic;
198 unsigned int pr_prog_addr;
199 unsigned int pr_reh_addr;
200 unsigned int pr_magic;
201 unsigned int rsu_update_counter;
202 };
203
204 /**
205 * struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information
206 * @cells: MFD cells
207 * @n_cells: MFD cells ARRAY_SIZE()
208 * @csr_map: the mappings for register definition of MAX10 BMC
209 */
210 struct intel_m10bmc_platform_info {
211 struct mfd_cell *cells;
212 int n_cells;
213 const struct m10bmc_csr_map *csr_map;
214 };
215
216 struct intel_m10bmc;
217
218 /**
219 * struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W
220 * @read: read a block of data from flash
221 * @write: write a block of data to flash
222 * @lock_write: locks flash access for erase+write
223 * @unlock_write: unlock flash access
224 *
225 * Write must be protected with @lock_write and @unlock_write. While the flash
226 * is locked, @read returns -EBUSY.
227 */
228 struct intel_m10bmc_flash_bulk_ops {
229 int (*read)(struct intel_m10bmc *m10bmc, u8 *buf, u32 addr, u32 size);
230 int (*write)(struct intel_m10bmc *m10bmc, const u8 *buf, u32 offset, u32 size);
231 int (*lock_write)(struct intel_m10bmc *m10bmc);
232 void (*unlock_write)(struct intel_m10bmc *m10bmc);
233 };
234
235 /**
236 * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
237 * @dev: this device
238 * @regmap: the regmap used to access registers by m10bmc itself
239 * @info: the platform information for MAX10 BMC
240 * @flash_bulk_ops: optional device specific operations for flash R/W
241 */
242 struct intel_m10bmc {
243 struct device *dev;
244 struct regmap *regmap;
245 const struct intel_m10bmc_platform_info *info;
246 const struct intel_m10bmc_flash_bulk_ops *flash_bulk_ops;
247 };
248
249 /*
250 * register access helper functions.
251 *
252 * m10bmc_raw_read - read m10bmc register per addr
253 * m10bmc_sys_read - read m10bmc system register per offset
254 */
255 static inline int
m10bmc_raw_read(struct intel_m10bmc * m10bmc,unsigned int addr,unsigned int * val)256 m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
257 unsigned int *val)
258 {
259 int ret;
260
261 ret = regmap_read(m10bmc->regmap, addr, val);
262 if (ret)
263 dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
264 addr, ret);
265
266 return ret;
267 }
268
269 /*
270 * The base of the system registers could be configured by HW developers, and
271 * in HW SPEC, the base is not added to the addresses of the system registers.
272 *
273 * This function helps to simplify the accessing of the system registers. And if
274 * the base is reconfigured in HW, SW developers could simply change the
275 * csr_map's base accordingly.
276 */
m10bmc_sys_read(struct intel_m10bmc * m10bmc,unsigned int offset,unsigned int * val)277 static inline int m10bmc_sys_read(struct intel_m10bmc *m10bmc, unsigned int offset,
278 unsigned int *val)
279 {
280 const struct m10bmc_csr_map *csr_map = m10bmc->info->csr_map;
281
282 return m10bmc_raw_read(m10bmc, csr_map->base + offset, val);
283 }
284
285 /*
286 * MAX10 BMC Core support
287 */
288 int m10bmc_dev_init(struct intel_m10bmc *m10bmc, const struct intel_m10bmc_platform_info *info);
289 extern const struct attribute_group *m10bmc_dev_groups[];
290
291 #endif /* __MFD_INTEL_M10_BMC_H */
292