| /linux-6.3-rc2/include/dt-bindings/clock/ |
| A D | exynos7-clk.h | 98 #define SCLK_UART3 6 macro
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| A D | s5pv210.h | 194 #define SCLK_UART3 172 macro
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| A D | rk3188-cru-common.h | 23 #define SCLK_UART3 67 macro
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| A D | px30-cru.h | 28 #define SCLK_UART3 26 macro
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| A D | rk3288-cru.h | 35 #define SCLK_UART3 80 macro
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| A D | rk3308-cru.h | 24 #define SCLK_UART3 20 macro
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| A D | rk3368-cru.h | 33 #define SCLK_UART3 80 macro
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| A D | rockchip,rv1126-cru.h | 90 #define SCLK_UART3 24 macro
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| A D | rk3399-cru.h | 41 #define SCLK_UART3 84 macro
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| A D | rockchip,rk3588-cru.h | 194 #define SCLK_UART3 179 macro
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| A D | rk3568-cru.h | 358 #define SCLK_UART3 295 macro
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| /linux-6.3-rc2/drivers/clk/samsung/ |
| A D | clk-s5pv210.c | 675 GATE(SCLK_UART3, "sclk_uart3", "dout_uart3", CLK_SRC_MASK0, 15,
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| A D | clk-exynos7.c | 782 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
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| /linux-6.3-rc2/arch/arm/boot/dts/ |
| A D | rk3xxx.dtsi | 435 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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| A D | rv1126.dtsi | 272 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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| A D | s5pv210.dtsi | 356 <&clocks SCLK_UART3>;
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| /linux-6.3-rc2/drivers/clk/rockchip/ |
| A D | clk-rk3188.c | 272 MUX(SCLK_UART3, "sclk_uart3", mux_sclk_uart3_p, CLK_SET_RATE_PARENT,
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| A D | clk-rk3368.c | 267 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
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| A D | clk-rk3288.c | 275 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
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| A D | clk-px30.c | 697 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", CLK_SET_RATE_PARENT,
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| A D | clk-rk3308.c | 367 GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
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| A D | clk-rv1126.c | 483 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
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| A D | clk-rk3399.c | 274 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
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| A D | clk-rk3568.c | 1232 GATE(SCLK_UART3, "sclk_uart3", "sclk_uart3_mux", 0,
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| /linux-6.3-rc2/arch/arm64/boot/dts/exynos/ |
| A D | exynos7.dtsi | 317 <&clock_peric1 SCLK_UART3>;
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