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Searched refs:SDMA0_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dsdma_v3_0.c580 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
582 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
591 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
593 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v3_0_ctx_switch_enable()
1343 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1348 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1359 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1364 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
A Dsdma_v2_4.c1009 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1014 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1025 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1030 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
A Dsdma_v5_2.c440 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_2_ctx_switch_enable()
581 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v5_2_gfx_resume()
584 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); in sdma_v5_2_gfx_resume()
1406 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_2_set_trap_irq_state()
A Dsdma_v5_0.c628 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v5_0_ctx_switch_enable()
783 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v5_0_gfx_resume()
786 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); in sdma_v5_0_gfx_resume()
1558 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_0_set_trap_irq_state()
A Dcik_sdma.c373 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
382 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in cik_ctx_switch_enable()
A Dsdma_v4_0.c967 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, in sdma_v4_0_ctx_switch_enable()
1373 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); in sdma_v4_0_start()
1997 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
A Dsdma_v6_0.c1430 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v6_0_set_trap_irq_state()
/linux-6.3-rc2/drivers/gpu/drm/radeon/
A Dcik_reg.h204 #define SDMA0_CNTL 0xD010 macro
A Dcik_sdma.c313 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
318 WREG32(SDMA0_CNTL + reg_offset, value); in cik_sdma_ctx_switch_enable()
A Dcik.c6863 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6864 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
6865 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6866 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
7048 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7049 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7219 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set()
7220 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
A Dcikd.h1960 #define SDMA0_CNTL 0xD010 macro

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