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Searched refs:SDMA0_PHASE0_QUANTUM__UNIT__SHIFT (Results 1 – 16 of 16) sorted by relevance

/linux-6.3-rc2/drivers/gpu/drm/amd/amdgpu/
A Dcik_sdma.c356 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { in cik_ctx_switch_enable()
360 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); in cik_ctx_switch_enable()
367 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; in cik_ctx_switch_enable()
A Dsdma_v3_0.c563 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { in sdma_v3_0_ctx_switch_enable()
567 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); in sdma_v3_0_ctx_switch_enable()
574 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; in sdma_v3_0_ctx_switch_enable()
A Dsdma_v5_2.c414 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { in sdma_v5_2_ctx_switch_enable()
418 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); in sdma_v5_2_ctx_switch_enable()
425 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; in sdma_v5_2_ctx_switch_enable()
A Dsdma_v5_0.c611 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { in sdma_v5_0_ctx_switch_enable()
615 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); in sdma_v5_0_ctx_switch_enable()
622 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; in sdma_v5_0_ctx_switch_enable()
A Dsdma_v4_0.c951 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { in sdma_v4_0_ctx_switch_enable()
955 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); in sdma_v4_0_ctx_switch_enable()
962 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; in sdma_v4_0_ctx_switch_enable()
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/sdma0/
A Dsdma0_4_1_sh_mask.h595 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT … macro
A Dsdma0_4_0_sh_mask.h596 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 macro
A Dsdma0_4_2_sh_mask.h598 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT … macro
A Dsdma0_4_2_2_sh_mask.h604 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT … macro
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/oss/
A Doss_2_0_sh_mask.h1012 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 macro
A Doss_2_4_sh_mask.h1102 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 macro
A Doss_3_0_1_sh_mask.h1122 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 macro
A Doss_3_0_sh_mask.h1628 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 macro
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/sdma/
A Dsdma_4_4_0_sh_mask.h291 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT … macro
/linux-6.3-rc2/drivers/gpu/drm/amd/include/asic_reg/gc/
A Dgc_10_1_0_sh_mask.h310 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT … macro
A Dgc_10_3_0_sh_mask.h311 #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT … macro

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