1 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
2 /*
3 * Copyright(c) 2015 - 2018 Intel Corporation.
4 */
5
6 #ifndef _HFI1_SDMA_H
7 #define _HFI1_SDMA_H
8
9 #include <linux/types.h>
10 #include <linux/list.h>
11 #include <asm/byteorder.h>
12 #include <linux/workqueue.h>
13 #include <linux/rculist.h>
14
15 #include "hfi.h"
16 #include "verbs.h"
17 #include "sdma_txreq.h"
18
19 /* Hardware limit */
20 #define MAX_DESC 64
21 /* Hardware limit for SDMA packet size */
22 #define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1)
23
24 #define SDMA_MAP_NONE 0
25 #define SDMA_MAP_SINGLE 1
26 #define SDMA_MAP_PAGE 2
27
28 #define SDMA_AHG_VALUE_MASK 0xffff
29 #define SDMA_AHG_VALUE_SHIFT 0
30 #define SDMA_AHG_INDEX_MASK 0xf
31 #define SDMA_AHG_INDEX_SHIFT 16
32 #define SDMA_AHG_FIELD_LEN_MASK 0xf
33 #define SDMA_AHG_FIELD_LEN_SHIFT 20
34 #define SDMA_AHG_FIELD_START_MASK 0x1f
35 #define SDMA_AHG_FIELD_START_SHIFT 24
36 #define SDMA_AHG_UPDATE_ENABLE_MASK 0x1
37 #define SDMA_AHG_UPDATE_ENABLE_SHIFT 31
38
39 /* AHG modes */
40
41 /*
42 * Be aware the ordering and values
43 * for SDMA_AHG_APPLY_UPDATE[123]
44 * are assumed in generating a skip
45 * count in submit_tx() in sdma.c
46 */
47 #define SDMA_AHG_NO_AHG 0
48 #define SDMA_AHG_COPY 1
49 #define SDMA_AHG_APPLY_UPDATE1 2
50 #define SDMA_AHG_APPLY_UPDATE2 3
51 #define SDMA_AHG_APPLY_UPDATE3 4
52
53 /*
54 * Bits defined in the send DMA descriptor.
55 */
56 #define SDMA_DESC0_FIRST_DESC_FLAG BIT_ULL(63)
57 #define SDMA_DESC0_LAST_DESC_FLAG BIT_ULL(62)
58 #define SDMA_DESC0_BYTE_COUNT_SHIFT 48
59 #define SDMA_DESC0_BYTE_COUNT_WIDTH 14
60 #define SDMA_DESC0_BYTE_COUNT_MASK \
61 ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1)
62 #define SDMA_DESC0_BYTE_COUNT_SMASK \
63 (SDMA_DESC0_BYTE_COUNT_MASK << SDMA_DESC0_BYTE_COUNT_SHIFT)
64 #define SDMA_DESC0_PHY_ADDR_SHIFT 0
65 #define SDMA_DESC0_PHY_ADDR_WIDTH 48
66 #define SDMA_DESC0_PHY_ADDR_MASK \
67 ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1)
68 #define SDMA_DESC0_PHY_ADDR_SMASK \
69 (SDMA_DESC0_PHY_ADDR_MASK << SDMA_DESC0_PHY_ADDR_SHIFT)
70
71 #define SDMA_DESC1_HEADER_UPDATE1_SHIFT 32
72 #define SDMA_DESC1_HEADER_UPDATE1_WIDTH 32
73 #define SDMA_DESC1_HEADER_UPDATE1_MASK \
74 ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1)
75 #define SDMA_DESC1_HEADER_UPDATE1_SMASK \
76 (SDMA_DESC1_HEADER_UPDATE1_MASK << SDMA_DESC1_HEADER_UPDATE1_SHIFT)
77 #define SDMA_DESC1_HEADER_MODE_SHIFT 13
78 #define SDMA_DESC1_HEADER_MODE_WIDTH 3
79 #define SDMA_DESC1_HEADER_MODE_MASK \
80 ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1)
81 #define SDMA_DESC1_HEADER_MODE_SMASK \
82 (SDMA_DESC1_HEADER_MODE_MASK << SDMA_DESC1_HEADER_MODE_SHIFT)
83 #define SDMA_DESC1_HEADER_INDEX_SHIFT 8
84 #define SDMA_DESC1_HEADER_INDEX_WIDTH 5
85 #define SDMA_DESC1_HEADER_INDEX_MASK \
86 ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1)
87 #define SDMA_DESC1_HEADER_INDEX_SMASK \
88 (SDMA_DESC1_HEADER_INDEX_MASK << SDMA_DESC1_HEADER_INDEX_SHIFT)
89 #define SDMA_DESC1_HEADER_DWS_SHIFT 4
90 #define SDMA_DESC1_HEADER_DWS_WIDTH 4
91 #define SDMA_DESC1_HEADER_DWS_MASK \
92 ((1ULL << SDMA_DESC1_HEADER_DWS_WIDTH) - 1)
93 #define SDMA_DESC1_HEADER_DWS_SMASK \
94 (SDMA_DESC1_HEADER_DWS_MASK << SDMA_DESC1_HEADER_DWS_SHIFT)
95 #define SDMA_DESC1_GENERATION_SHIFT 2
96 #define SDMA_DESC1_GENERATION_WIDTH 2
97 #define SDMA_DESC1_GENERATION_MASK \
98 ((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1)
99 #define SDMA_DESC1_GENERATION_SMASK \
100 (SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT)
101 #define SDMA_DESC1_INT_REQ_FLAG BIT_ULL(1)
102 #define SDMA_DESC1_HEAD_TO_HOST_FLAG BIT_ULL(0)
103
104 enum sdma_states {
105 sdma_state_s00_hw_down,
106 sdma_state_s10_hw_start_up_halt_wait,
107 sdma_state_s15_hw_start_up_clean_wait,
108 sdma_state_s20_idle,
109 sdma_state_s30_sw_clean_up_wait,
110 sdma_state_s40_hw_clean_up_wait,
111 sdma_state_s50_hw_halt_wait,
112 sdma_state_s60_idle_halt_wait,
113 sdma_state_s80_hw_freeze,
114 sdma_state_s82_freeze_sw_clean,
115 sdma_state_s99_running,
116 };
117
118 enum sdma_events {
119 sdma_event_e00_go_hw_down,
120 sdma_event_e10_go_hw_start,
121 sdma_event_e15_hw_halt_done,
122 sdma_event_e25_hw_clean_up_done,
123 sdma_event_e30_go_running,
124 sdma_event_e40_sw_cleaned,
125 sdma_event_e50_hw_cleaned,
126 sdma_event_e60_hw_halted,
127 sdma_event_e70_go_idle,
128 sdma_event_e80_hw_freeze,
129 sdma_event_e81_hw_frozen,
130 sdma_event_e82_hw_unfreeze,
131 sdma_event_e85_link_down,
132 sdma_event_e90_sw_halted,
133 };
134
135 struct sdma_set_state_action {
136 unsigned op_enable:1;
137 unsigned op_intenable:1;
138 unsigned op_halt:1;
139 unsigned op_cleanup:1;
140 unsigned go_s99_running_tofalse:1;
141 unsigned go_s99_running_totrue:1;
142 };
143
144 struct sdma_state {
145 struct kref kref;
146 struct completion comp;
147 enum sdma_states current_state;
148 unsigned current_op;
149 unsigned go_s99_running;
150 /* debugging/development */
151 enum sdma_states previous_state;
152 unsigned previous_op;
153 enum sdma_events last_event;
154 };
155
156 /**
157 * DOC: sdma exported routines
158 *
159 * These sdma routines fit into three categories:
160 * - The SDMA API for building and submitting packets
161 * to the ring
162 *
163 * - Initialization and tear down routines to buildup
164 * and tear down SDMA
165 *
166 * - ISR entrances to handle interrupts, state changes
167 * and errors
168 */
169
170 /**
171 * DOC: sdma PSM/verbs API
172 *
173 * The sdma API is designed to be used by both PSM
174 * and verbs to supply packets to the SDMA ring.
175 *
176 * The usage of the API is as follows:
177 *
178 * Embed a struct iowait in the QP or
179 * PQ. The iowait should be initialized with a
180 * call to iowait_init().
181 *
182 * The user of the API should create an allocation method
183 * for their version of the txreq. slabs, pre-allocated lists,
184 * and dma pools can be used. Once the user's overload of
185 * the sdma_txreq has been allocated, the sdma_txreq member
186 * must be initialized with sdma_txinit() or sdma_txinit_ahg().
187 *
188 * The txreq must be declared with the sdma_txreq first.
189 *
190 * The tx request, once initialized, is manipulated with calls to
191 * sdma_txadd_daddr(), sdma_txadd_page(), or sdma_txadd_kvaddr()
192 * for each disjoint memory location. It is the user's responsibility
193 * to understand the packet boundaries and page boundaries to do the
194 * appropriate number of sdma_txadd_* calls.. The user
195 * must be prepared to deal with failures from these routines due to
196 * either memory allocation or dma_mapping failures.
197 *
198 * The mapping specifics for each memory location are recorded
199 * in the tx. Memory locations added with sdma_txadd_page()
200 * and sdma_txadd_kvaddr() are automatically mapped when added
201 * to the tx and nmapped as part of the progress processing in the
202 * SDMA interrupt handling.
203 *
204 * sdma_txadd_daddr() is used to add an dma_addr_t memory to the
205 * tx. An example of a use case would be a pre-allocated
206 * set of headers allocated via dma_pool_alloc() or
207 * dma_alloc_coherent(). For these memory locations, it
208 * is the responsibility of the user to handle that unmapping.
209 * (This would usually be at an unload or job termination.)
210 *
211 * The routine sdma_send_txreq() is used to submit
212 * a tx to the ring after the appropriate number of
213 * sdma_txadd_* have been done.
214 *
215 * If it is desired to send a burst of sdma_txreqs, sdma_send_txlist()
216 * can be used to submit a list of packets.
217 *
218 * The user is free to use the link overhead in the struct sdma_txreq as
219 * long as the tx isn't in flight.
220 *
221 * The extreme degenerate case of the number of descriptors
222 * exceeding the ring size is automatically handled as
223 * memory locations are added. An overflow of the descriptor
224 * array that is part of the sdma_txreq is also automatically
225 * handled.
226 *
227 */
228
229 /**
230 * DOC: Infrastructure calls
231 *
232 * sdma_init() is used to initialize data structures and
233 * CSRs for the desired number of SDMA engines.
234 *
235 * sdma_start() is used to kick the SDMA engines initialized
236 * with sdma_init(). Interrupts must be enabled at this
237 * point since aspects of the state machine are interrupt
238 * driven.
239 *
240 * sdma_engine_error() and sdma_engine_interrupt() are
241 * entrances for interrupts.
242 *
243 * sdma_map_init() is for the management of the mapping
244 * table when the number of vls is changed.
245 *
246 */
247
248 /*
249 * struct hw_sdma_desc - raw 128 bit SDMA descriptor
250 *
251 * This is the raw descriptor in the SDMA ring
252 */
253 struct hw_sdma_desc {
254 /* private: don't use directly */
255 __le64 qw[2];
256 };
257
258 /**
259 * struct sdma_engine - Data pertaining to each SDMA engine.
260 * @dd: a back-pointer to the device data
261 * @ppd: per port back-pointer
262 * @imask: mask for irq manipulation
263 * @idle_mask: mask for determining if an interrupt is due to sdma_idle
264 *
265 * This structure has the state for each sdma_engine.
266 *
267 * Accessing to non public fields are not supported
268 * since the private members are subject to change.
269 */
270 struct sdma_engine {
271 /* read mostly */
272 struct hfi1_devdata *dd;
273 struct hfi1_pportdata *ppd;
274 /* private: */
275 void __iomem *tail_csr;
276 u64 imask; /* clear interrupt mask */
277 u64 idle_mask;
278 u64 progress_mask;
279 u64 int_mask;
280 /* private: */
281 volatile __le64 *head_dma; /* DMA'ed by chip */
282 /* private: */
283 dma_addr_t head_phys;
284 /* private: */
285 struct hw_sdma_desc *descq;
286 /* private: */
287 unsigned descq_full_count;
288 struct sdma_txreq **tx_ring;
289 /* private: */
290 dma_addr_t descq_phys;
291 /* private */
292 u32 sdma_mask;
293 /* private */
294 struct sdma_state state;
295 /* private */
296 int cpu;
297 /* private: */
298 u8 sdma_shift;
299 /* private: */
300 u8 this_idx; /* zero relative engine */
301 /* protect changes to senddmactrl shadow */
302 spinlock_t senddmactrl_lock;
303 /* private: */
304 u64 p_senddmactrl; /* shadow per-engine SendDmaCtrl */
305
306 /* read/write using tail_lock */
307 spinlock_t tail_lock ____cacheline_aligned_in_smp;
308 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
309 /* private: */
310 u64 tail_sn;
311 #endif
312 /* private: */
313 u32 descq_tail;
314 /* private: */
315 unsigned long ahg_bits;
316 /* private: */
317 u16 desc_avail;
318 /* private: */
319 u16 tx_tail;
320 /* private: */
321 u16 descq_cnt;
322
323 /* read/write using head_lock */
324 /* private: */
325 seqlock_t head_lock ____cacheline_aligned_in_smp;
326 #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
327 /* private: */
328 u64 head_sn;
329 #endif
330 /* private: */
331 u32 descq_head;
332 /* private: */
333 u16 tx_head;
334 /* private: */
335 u64 last_status;
336 /* private */
337 u64 err_cnt;
338 /* private */
339 u64 sdma_int_cnt;
340 u64 idle_int_cnt;
341 u64 progress_int_cnt;
342
343 /* private: */
344 seqlock_t waitlock;
345 struct list_head dmawait;
346
347 /* CONFIG SDMA for now, just blindly duplicate */
348 /* private: */
349 struct tasklet_struct sdma_hw_clean_up_task
350 ____cacheline_aligned_in_smp;
351
352 /* private: */
353 struct tasklet_struct sdma_sw_clean_up_task
354 ____cacheline_aligned_in_smp;
355 /* private: */
356 struct work_struct err_halt_worker;
357 /* private */
358 struct timer_list err_progress_check_timer;
359 u32 progress_check_head;
360 /* private: */
361 struct work_struct flush_worker;
362 /* protect flush list */
363 spinlock_t flushlist_lock;
364 /* private: */
365 struct list_head flushlist;
366 struct cpumask cpu_mask;
367 struct kobject kobj;
368 u32 msix_intr;
369 };
370
371 int sdma_init(struct hfi1_devdata *dd, u8 port);
372 void sdma_start(struct hfi1_devdata *dd);
373 void sdma_exit(struct hfi1_devdata *dd);
374 void sdma_clean(struct hfi1_devdata *dd, size_t num_engines);
375 void sdma_all_running(struct hfi1_devdata *dd);
376 void sdma_all_idle(struct hfi1_devdata *dd);
377 void sdma_freeze_notify(struct hfi1_devdata *dd, int go_idle);
378 void sdma_freeze(struct hfi1_devdata *dd);
379 void sdma_unfreeze(struct hfi1_devdata *dd);
380 void sdma_wait(struct hfi1_devdata *dd);
381
382 /**
383 * sdma_empty() - idle engine test
384 * @engine: sdma engine
385 *
386 * Currently used by verbs as a latency optimization.
387 *
388 * Return:
389 * 1 - empty, 0 - non-empty
390 */
sdma_empty(struct sdma_engine * sde)391 static inline int sdma_empty(struct sdma_engine *sde)
392 {
393 return sde->descq_tail == sde->descq_head;
394 }
395
sdma_descq_freecnt(struct sdma_engine * sde)396 static inline u16 sdma_descq_freecnt(struct sdma_engine *sde)
397 {
398 return sde->descq_cnt -
399 (sde->descq_tail -
400 READ_ONCE(sde->descq_head)) - 1;
401 }
402
sdma_descq_inprocess(struct sdma_engine * sde)403 static inline u16 sdma_descq_inprocess(struct sdma_engine *sde)
404 {
405 return sde->descq_cnt - sdma_descq_freecnt(sde);
406 }
407
408 /*
409 * Either head_lock or tail lock required to see
410 * a steady state.
411 */
__sdma_running(struct sdma_engine * engine)412 static inline int __sdma_running(struct sdma_engine *engine)
413 {
414 return engine->state.current_state == sdma_state_s99_running;
415 }
416
417 /**
418 * sdma_running() - state suitability test
419 * @engine: sdma engine
420 *
421 * sdma_running probes the internal state to determine if it is suitable
422 * for submitting packets.
423 *
424 * Return:
425 * 1 - ok to submit, 0 - not ok to submit
426 *
427 */
sdma_running(struct sdma_engine * engine)428 static inline int sdma_running(struct sdma_engine *engine)
429 {
430 unsigned long flags;
431 int ret;
432
433 spin_lock_irqsave(&engine->tail_lock, flags);
434 ret = __sdma_running(engine);
435 spin_unlock_irqrestore(&engine->tail_lock, flags);
436 return ret;
437 }
438
439 void _sdma_txreq_ahgadd(
440 struct sdma_txreq *tx,
441 u8 num_ahg,
442 u8 ahg_entry,
443 u32 *ahg,
444 u8 ahg_hlen);
445
446 /**
447 * sdma_txinit_ahg() - initialize an sdma_txreq struct with AHG
448 * @tx: tx request to initialize
449 * @flags: flags to key last descriptor additions
450 * @tlen: total packet length (pbc + headers + data)
451 * @ahg_entry: ahg entry to use (0 - 31)
452 * @num_ahg: ahg descriptor for first descriptor (0 - 9)
453 * @ahg: array of AHG descriptors (up to 9 entries)
454 * @ahg_hlen: number of bytes from ASIC entry to use
455 * @cb: callback
456 *
457 * The allocation of the sdma_txreq and it enclosing structure is user
458 * dependent. This routine must be called to initialize the user independent
459 * fields.
460 *
461 * The currently supported flags are SDMA_TXREQ_F_URGENT,
462 * SDMA_TXREQ_F_AHG_COPY, and SDMA_TXREQ_F_USE_AHG.
463 *
464 * SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the
465 * completion is desired as soon as possible.
466 *
467 * SDMA_TXREQ_F_AHG_COPY causes the header in the first descriptor to be
468 * copied to chip entry. SDMA_TXREQ_F_USE_AHG causes the code to add in
469 * the AHG descriptors into the first 1 to 3 descriptors.
470 *
471 * Completions of submitted requests can be gotten on selected
472 * txreqs by giving a completion routine callback to sdma_txinit() or
473 * sdma_txinit_ahg(). The environment in which the callback runs
474 * can be from an ISR, a tasklet, or a thread, so no sleeping
475 * kernel routines can be used. Aspects of the sdma ring may
476 * be locked so care should be taken with locking.
477 *
478 * The callback pointer can be NULL to avoid any callback for the packet
479 * being submitted. The callback will be provided this tx, a status, and a flag.
480 *
481 * The status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR,
482 * SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN.
483 *
484 * The flag, if the is the iowait had been used, indicates the iowait
485 * sdma_busy count has reached zero.
486 *
487 * user data portion of tlen should be precise. The sdma_txadd_* entrances
488 * will pad with a descriptor references 1 - 3 bytes when the number of bytes
489 * specified in tlen have been supplied to the sdma_txreq.
490 *
491 * ahg_hlen is used to determine the number of on-chip entry bytes to
492 * use as the header. This is for cases where the stored header is
493 * larger than the header to be used in a packet. This is typical
494 * for verbs where an RDMA_WRITE_FIRST is larger than the packet in
495 * and RDMA_WRITE_MIDDLE.
496 *
497 */
sdma_txinit_ahg(struct sdma_txreq * tx,u16 flags,u16 tlen,u8 ahg_entry,u8 num_ahg,u32 * ahg,u8 ahg_hlen,void (* cb)(struct sdma_txreq *,int))498 static inline int sdma_txinit_ahg(
499 struct sdma_txreq *tx,
500 u16 flags,
501 u16 tlen,
502 u8 ahg_entry,
503 u8 num_ahg,
504 u32 *ahg,
505 u8 ahg_hlen,
506 void (*cb)(struct sdma_txreq *, int))
507 {
508 if (tlen == 0)
509 return -ENODATA;
510 if (tlen > MAX_SDMA_PKT_SIZE)
511 return -EMSGSIZE;
512 tx->desc_limit = ARRAY_SIZE(tx->descs);
513 tx->descp = &tx->descs[0];
514 INIT_LIST_HEAD(&tx->list);
515 tx->num_desc = 0;
516 tx->flags = flags;
517 tx->complete = cb;
518 tx->coalesce_buf = NULL;
519 tx->wait = NULL;
520 tx->packet_len = tlen;
521 tx->tlen = tx->packet_len;
522 tx->descs[0].qw[0] = SDMA_DESC0_FIRST_DESC_FLAG;
523 tx->descs[0].qw[1] = 0;
524 if (flags & SDMA_TXREQ_F_AHG_COPY)
525 tx->descs[0].qw[1] |=
526 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)
527 << SDMA_DESC1_HEADER_INDEX_SHIFT) |
528 (((u64)SDMA_AHG_COPY & SDMA_DESC1_HEADER_MODE_MASK)
529 << SDMA_DESC1_HEADER_MODE_SHIFT);
530 else if (flags & SDMA_TXREQ_F_USE_AHG && num_ahg)
531 _sdma_txreq_ahgadd(tx, num_ahg, ahg_entry, ahg, ahg_hlen);
532 return 0;
533 }
534
535 /**
536 * sdma_txinit() - initialize an sdma_txreq struct (no AHG)
537 * @tx: tx request to initialize
538 * @flags: flags to key last descriptor additions
539 * @tlen: total packet length (pbc + headers + data)
540 * @cb: callback pointer
541 *
542 * The allocation of the sdma_txreq and it enclosing structure is user
543 * dependent. This routine must be called to initialize the user
544 * independent fields.
545 *
546 * The currently supported flags is SDMA_TXREQ_F_URGENT.
547 *
548 * SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the
549 * completion is desired as soon as possible.
550 *
551 * Completions of submitted requests can be gotten on selected
552 * txreqs by giving a completion routine callback to sdma_txinit() or
553 * sdma_txinit_ahg(). The environment in which the callback runs
554 * can be from an ISR, a tasklet, or a thread, so no sleeping
555 * kernel routines can be used. The head size of the sdma ring may
556 * be locked so care should be taken with locking.
557 *
558 * The callback pointer can be NULL to avoid any callback for the packet
559 * being submitted.
560 *
561 * The callback, if non-NULL, will be provided this tx and a status. The
562 * status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR,
563 * SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN.
564 *
565 */
sdma_txinit(struct sdma_txreq * tx,u16 flags,u16 tlen,void (* cb)(struct sdma_txreq *,int))566 static inline int sdma_txinit(
567 struct sdma_txreq *tx,
568 u16 flags,
569 u16 tlen,
570 void (*cb)(struct sdma_txreq *, int))
571 {
572 return sdma_txinit_ahg(tx, flags, tlen, 0, 0, NULL, 0, cb);
573 }
574
575 /* helpers - don't use */
sdma_mapping_type(struct sdma_desc * d)576 static inline int sdma_mapping_type(struct sdma_desc *d)
577 {
578 return (d->qw[1] & SDMA_DESC1_GENERATION_SMASK)
579 >> SDMA_DESC1_GENERATION_SHIFT;
580 }
581
sdma_mapping_len(struct sdma_desc * d)582 static inline size_t sdma_mapping_len(struct sdma_desc *d)
583 {
584 return (d->qw[0] & SDMA_DESC0_BYTE_COUNT_SMASK)
585 >> SDMA_DESC0_BYTE_COUNT_SHIFT;
586 }
587
sdma_mapping_addr(struct sdma_desc * d)588 static inline dma_addr_t sdma_mapping_addr(struct sdma_desc *d)
589 {
590 return (d->qw[0] & SDMA_DESC0_PHY_ADDR_SMASK)
591 >> SDMA_DESC0_PHY_ADDR_SHIFT;
592 }
593
make_tx_sdma_desc(struct sdma_txreq * tx,int type,dma_addr_t addr,size_t len)594 static inline void make_tx_sdma_desc(
595 struct sdma_txreq *tx,
596 int type,
597 dma_addr_t addr,
598 size_t len)
599 {
600 struct sdma_desc *desc = &tx->descp[tx->num_desc];
601
602 if (!tx->num_desc) {
603 /* qw[0] zero; qw[1] first, ahg mode already in from init */
604 desc->qw[1] |= ((u64)type & SDMA_DESC1_GENERATION_MASK)
605 << SDMA_DESC1_GENERATION_SHIFT;
606 } else {
607 desc->qw[0] = 0;
608 desc->qw[1] = ((u64)type & SDMA_DESC1_GENERATION_MASK)
609 << SDMA_DESC1_GENERATION_SHIFT;
610 }
611 desc->qw[0] |= (((u64)addr & SDMA_DESC0_PHY_ADDR_MASK)
612 << SDMA_DESC0_PHY_ADDR_SHIFT) |
613 (((u64)len & SDMA_DESC0_BYTE_COUNT_MASK)
614 << SDMA_DESC0_BYTE_COUNT_SHIFT);
615 }
616
617 /* helper to extend txreq */
618 int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,
619 int type, void *kvaddr, struct page *page,
620 unsigned long offset, u16 len);
621 int _pad_sdma_tx_descs(struct hfi1_devdata *, struct sdma_txreq *);
622 void __sdma_txclean(struct hfi1_devdata *, struct sdma_txreq *);
623
sdma_txclean(struct hfi1_devdata * dd,struct sdma_txreq * tx)624 static inline void sdma_txclean(struct hfi1_devdata *dd, struct sdma_txreq *tx)
625 {
626 if (tx->num_desc)
627 __sdma_txclean(dd, tx);
628 }
629
630 /* helpers used by public routines */
_sdma_close_tx(struct hfi1_devdata * dd,struct sdma_txreq * tx)631 static inline void _sdma_close_tx(struct hfi1_devdata *dd,
632 struct sdma_txreq *tx)
633 {
634 u16 last_desc = tx->num_desc - 1;
635
636 tx->descp[last_desc].qw[0] |= SDMA_DESC0_LAST_DESC_FLAG;
637 tx->descp[last_desc].qw[1] |= dd->default_desc1;
638 if (tx->flags & SDMA_TXREQ_F_URGENT)
639 tx->descp[last_desc].qw[1] |= (SDMA_DESC1_HEAD_TO_HOST_FLAG |
640 SDMA_DESC1_INT_REQ_FLAG);
641 }
642
_sdma_txadd_daddr(struct hfi1_devdata * dd,int type,struct sdma_txreq * tx,dma_addr_t addr,u16 len)643 static inline int _sdma_txadd_daddr(
644 struct hfi1_devdata *dd,
645 int type,
646 struct sdma_txreq *tx,
647 dma_addr_t addr,
648 u16 len)
649 {
650 int rval = 0;
651
652 make_tx_sdma_desc(
653 tx,
654 type,
655 addr, len);
656 WARN_ON(len > tx->tlen);
657 tx->num_desc++;
658 tx->tlen -= len;
659 /* special cases for last */
660 if (!tx->tlen) {
661 if (tx->packet_len & (sizeof(u32) - 1)) {
662 rval = _pad_sdma_tx_descs(dd, tx);
663 if (rval)
664 return rval;
665 } else {
666 _sdma_close_tx(dd, tx);
667 }
668 }
669 return rval;
670 }
671
672 /**
673 * sdma_txadd_page() - add a page to the sdma_txreq
674 * @dd: the device to use for mapping
675 * @tx: tx request to which the page is added
676 * @page: page to map
677 * @offset: offset within the page
678 * @len: length in bytes
679 *
680 * This is used to add a page/offset/length descriptor.
681 *
682 * The mapping/unmapping of the page/offset/len is automatically handled.
683 *
684 * Return:
685 * 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't
686 * extend/coalesce descriptor array
687 */
sdma_txadd_page(struct hfi1_devdata * dd,struct sdma_txreq * tx,struct page * page,unsigned long offset,u16 len)688 static inline int sdma_txadd_page(
689 struct hfi1_devdata *dd,
690 struct sdma_txreq *tx,
691 struct page *page,
692 unsigned long offset,
693 u16 len)
694 {
695 dma_addr_t addr;
696 int rval;
697
698 if ((unlikely(tx->num_desc == tx->desc_limit))) {
699 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_PAGE,
700 NULL, page, offset, len);
701 if (rval <= 0)
702 return rval;
703 }
704
705 addr = dma_map_page(
706 &dd->pcidev->dev,
707 page,
708 offset,
709 len,
710 DMA_TO_DEVICE);
711
712 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
713 __sdma_txclean(dd, tx);
714 return -ENOSPC;
715 }
716
717 return _sdma_txadd_daddr(
718 dd, SDMA_MAP_PAGE, tx, addr, len);
719 }
720
721 /**
722 * sdma_txadd_daddr() - add a dma address to the sdma_txreq
723 * @dd: the device to use for mapping
724 * @tx: sdma_txreq to which the page is added
725 * @addr: dma address mapped by caller
726 * @len: length in bytes
727 *
728 * This is used to add a descriptor for memory that is already dma mapped.
729 *
730 * In this case, there is no unmapping as part of the progress processing for
731 * this memory location.
732 *
733 * Return:
734 * 0 - success, -ENOMEM - couldn't extend descriptor array
735 */
736
sdma_txadd_daddr(struct hfi1_devdata * dd,struct sdma_txreq * tx,dma_addr_t addr,u16 len)737 static inline int sdma_txadd_daddr(
738 struct hfi1_devdata *dd,
739 struct sdma_txreq *tx,
740 dma_addr_t addr,
741 u16 len)
742 {
743 int rval;
744
745 if ((unlikely(tx->num_desc == tx->desc_limit))) {
746 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_NONE,
747 NULL, NULL, 0, 0);
748 if (rval <= 0)
749 return rval;
750 }
751
752 return _sdma_txadd_daddr(dd, SDMA_MAP_NONE, tx, addr, len);
753 }
754
755 /**
756 * sdma_txadd_kvaddr() - add a kernel virtual address to sdma_txreq
757 * @dd: the device to use for mapping
758 * @tx: sdma_txreq to which the page is added
759 * @kvaddr: the kernel virtual address
760 * @len: length in bytes
761 *
762 * This is used to add a descriptor referenced by the indicated kvaddr and
763 * len.
764 *
765 * The mapping/unmapping of the kvaddr and len is automatically handled.
766 *
767 * Return:
768 * 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't extend/coalesce
769 * descriptor array
770 */
sdma_txadd_kvaddr(struct hfi1_devdata * dd,struct sdma_txreq * tx,void * kvaddr,u16 len)771 static inline int sdma_txadd_kvaddr(
772 struct hfi1_devdata *dd,
773 struct sdma_txreq *tx,
774 void *kvaddr,
775 u16 len)
776 {
777 dma_addr_t addr;
778 int rval;
779
780 if ((unlikely(tx->num_desc == tx->desc_limit))) {
781 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_SINGLE,
782 kvaddr, NULL, 0, len);
783 if (rval <= 0)
784 return rval;
785 }
786
787 addr = dma_map_single(
788 &dd->pcidev->dev,
789 kvaddr,
790 len,
791 DMA_TO_DEVICE);
792
793 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {
794 __sdma_txclean(dd, tx);
795 return -ENOSPC;
796 }
797
798 return _sdma_txadd_daddr(
799 dd, SDMA_MAP_SINGLE, tx, addr, len);
800 }
801
802 struct iowait_work;
803
804 int sdma_send_txreq(struct sdma_engine *sde,
805 struct iowait_work *wait,
806 struct sdma_txreq *tx,
807 bool pkts_sent);
808 int sdma_send_txlist(struct sdma_engine *sde,
809 struct iowait_work *wait,
810 struct list_head *tx_list,
811 u16 *count_out);
812
813 int sdma_ahg_alloc(struct sdma_engine *sde);
814 void sdma_ahg_free(struct sdma_engine *sde, int ahg_index);
815
816 /**
817 * sdma_build_ahg - build ahg descriptor
818 * @data
819 * @dwindex
820 * @startbit
821 * @bits
822 *
823 * Build and return a 32 bit descriptor.
824 */
sdma_build_ahg_descriptor(u16 data,u8 dwindex,u8 startbit,u8 bits)825 static inline u32 sdma_build_ahg_descriptor(
826 u16 data,
827 u8 dwindex,
828 u8 startbit,
829 u8 bits)
830 {
831 return (u32)(1UL << SDMA_AHG_UPDATE_ENABLE_SHIFT |
832 ((startbit & SDMA_AHG_FIELD_START_MASK) <<
833 SDMA_AHG_FIELD_START_SHIFT) |
834 ((bits & SDMA_AHG_FIELD_LEN_MASK) <<
835 SDMA_AHG_FIELD_LEN_SHIFT) |
836 ((dwindex & SDMA_AHG_INDEX_MASK) <<
837 SDMA_AHG_INDEX_SHIFT) |
838 ((data & SDMA_AHG_VALUE_MASK) <<
839 SDMA_AHG_VALUE_SHIFT));
840 }
841
842 /**
843 * sdma_progress - use seq number of detect head progress
844 * @sde: sdma_engine to check
845 * @seq: base seq count
846 * @tx: txreq for which we need to check descriptor availability
847 *
848 * This is used in the appropriate spot in the sleep routine
849 * to check for potential ring progress. This routine gets the
850 * seqcount before queuing the iowait structure for progress.
851 *
852 * If the seqcount indicates that progress needs to be checked,
853 * re-submission is detected by checking whether the descriptor
854 * queue has enough descriptor for the txreq.
855 */
sdma_progress(struct sdma_engine * sde,unsigned seq,struct sdma_txreq * tx)856 static inline unsigned sdma_progress(struct sdma_engine *sde, unsigned seq,
857 struct sdma_txreq *tx)
858 {
859 if (read_seqretry(&sde->head_lock, seq)) {
860 sde->desc_avail = sdma_descq_freecnt(sde);
861 if (tx->num_desc > sde->desc_avail)
862 return 0;
863 return 1;
864 }
865 return 0;
866 }
867
868 /* for use by interrupt handling */
869 void sdma_engine_error(struct sdma_engine *sde, u64 status);
870 void sdma_engine_interrupt(struct sdma_engine *sde, u64 status);
871
872 /*
873 *
874 * The diagram below details the relationship of the mapping structures
875 *
876 * Since the mapping now allows for non-uniform engines per vl, the
877 * number of engines for a vl is either the vl_engines[vl] or
878 * a computation based on num_sdma/num_vls:
879 *
880 * For example:
881 * nactual = vl_engines ? vl_engines[vl] : num_sdma/num_vls
882 *
883 * n = roundup to next highest power of 2 using nactual
884 *
885 * In the case where there are num_sdma/num_vls doesn't divide
886 * evenly, the extras are added from the last vl downward.
887 *
888 * For the case where n > nactual, the engines are assigned
889 * in a round robin fashion wrapping back to the first engine
890 * for a particular vl.
891 *
892 * dd->sdma_map
893 * | sdma_map_elem[0]
894 * | +--------------------+
895 * v | mask |
896 * sdma_vl_map |--------------------|
897 * +--------------------------+ | sde[0] -> eng 1 |
898 * | list (RCU) | |--------------------|
899 * |--------------------------| ->| sde[1] -> eng 2 |
900 * | mask | --/ |--------------------|
901 * |--------------------------| -/ | * |
902 * | actual_vls (max 8) | -/ |--------------------|
903 * |--------------------------| --/ | sde[n-1] -> eng n |
904 * | vls (max 8) | -/ +--------------------+
905 * |--------------------------| --/
906 * | map[0] |-/
907 * |--------------------------| +---------------------+
908 * | map[1] |--- | mask |
909 * |--------------------------| \---- |---------------------|
910 * | * | \-- | sde[0] -> eng 1+n |
911 * | * | \---- |---------------------|
912 * | * | \->| sde[1] -> eng 2+n |
913 * |--------------------------| |---------------------|
914 * | map[vls - 1] |- | * |
915 * +--------------------------+ \- |---------------------|
916 * \- | sde[m-1] -> eng m+n |
917 * \ +---------------------+
918 * \-
919 * \
920 * \- +----------------------+
921 * \- | mask |
922 * \ |----------------------|
923 * \- | sde[0] -> eng 1+m+n |
924 * \- |----------------------|
925 * >| sde[1] -> eng 2+m+n |
926 * |----------------------|
927 * | * |
928 * |----------------------|
929 * | sde[o-1] -> eng o+m+n|
930 * +----------------------+
931 *
932 */
933
934 /**
935 * struct sdma_map_elem - mapping for a vl
936 * @mask - selector mask
937 * @sde - array of engines for this vl
938 *
939 * The mask is used to "mod" the selector
940 * to produce index into the trailing
941 * array of sdes.
942 */
943 struct sdma_map_elem {
944 u32 mask;
945 struct sdma_engine *sde[];
946 };
947
948 /**
949 * struct sdma_map_el - mapping for a vl
950 * @engine_to_vl - map of an engine to a vl
951 * @list - rcu head for free callback
952 * @mask - vl mask to "mod" the vl to produce an index to map array
953 * @actual_vls - number of vls
954 * @vls - number of vls rounded to next power of 2
955 * @map - array of sdma_map_elem entries
956 *
957 * This is the parent mapping structure. The trailing
958 * members of the struct point to sdma_map_elem entries, which
959 * in turn point to an array of sde's for that vl.
960 */
961 struct sdma_vl_map {
962 s8 engine_to_vl[TXE_NUM_SDMA_ENGINES];
963 struct rcu_head list;
964 u32 mask;
965 u8 actual_vls;
966 u8 vls;
967 struct sdma_map_elem *map[];
968 };
969
970 int sdma_map_init(
971 struct hfi1_devdata *dd,
972 u8 port,
973 u8 num_vls,
974 u8 *vl_engines);
975
976 /* slow path */
977 void _sdma_engine_progress_schedule(struct sdma_engine *sde);
978
979 /**
980 * sdma_engine_progress_schedule() - schedule progress on engine
981 * @sde: sdma_engine to schedule progress
982 *
983 * This is the fast path.
984 *
985 */
sdma_engine_progress_schedule(struct sdma_engine * sde)986 static inline void sdma_engine_progress_schedule(
987 struct sdma_engine *sde)
988 {
989 if (!sde || sdma_descq_inprocess(sde) < (sde->descq_cnt / 8))
990 return;
991 _sdma_engine_progress_schedule(sde);
992 }
993
994 struct sdma_engine *sdma_select_engine_sc(
995 struct hfi1_devdata *dd,
996 u32 selector,
997 u8 sc5);
998
999 struct sdma_engine *sdma_select_engine_vl(
1000 struct hfi1_devdata *dd,
1001 u32 selector,
1002 u8 vl);
1003
1004 struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,
1005 u32 selector, u8 vl);
1006 ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf);
1007 ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf,
1008 size_t count);
1009 int sdma_engine_get_vl(struct sdma_engine *sde);
1010 void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *);
1011 void sdma_seqfile_dump_cpu_list(struct seq_file *s, struct hfi1_devdata *dd,
1012 unsigned long cpuid);
1013
1014 #ifdef CONFIG_SDMA_VERBOSITY
1015 void sdma_dumpstate(struct sdma_engine *);
1016 #endif
slashstrip(char * s)1017 static inline char *slashstrip(char *s)
1018 {
1019 char *r = s;
1020
1021 while (*s)
1022 if (*s++ == '/')
1023 r = s;
1024 return r;
1025 }
1026
1027 u16 sdma_get_descq_cnt(void);
1028
1029 extern uint mod_num_sdma;
1030
1031 void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid);
1032
1033 #endif
1034